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AMD did a presentation at the AI Advisory Council's 2019 conference back in September which had some slides showing the difference between EPYC Rome (Zen 2) and Milan (Zen 3). There was a diagram of the Zen 2 chiplet which showed 2 sets of 16MB L3 cache amongst the 8 cores and 8 lots of L2 cache. The Zen 3 chiplet diagram had a single block of 32+MB cache between the cores and L2. That could just mean AMD are slapping unified L3 cache across both CCXs to reduce latencies, or it could mean Zen 3 is updated to a single 8 core unit. So no it's not confirmed, but a single 8 core CCD is the rumour.
Not this gen, the next process node isn't that small. From what I understand, the chiplets can either go up slightly to 10 cores at the same size, stay at 8 cores at the same size but slightly less dense to improve thermals, or stay at 8 cores and shrink down a little.
AMD did a presentation at the AI Advisory Council's 2019 conference back in September which had some slides showing the difference between EPYC Rome (Zen 2) and Milan (Zen 3). There was a diagram of the Zen 2 chiplet which showed 2 sets of 16MB L3 cache amongst the 8 cores and 8 lots of L2 cache. The Zen 3 chiplet diagram had a single block of 32+MB cache between the cores and L2. That could just mean AMD are slapping unified L3 cache across both CCXs to reduce latencies, or it could mean Zen 3 is updated to a single 8 core unit. So no it's not confirmed, but a single 8 core CCD is the rumour.
OC3D article:
https://www.overclock3d.net/news/cp..._architecture_details_and_zen_4_genoa_plans/1
Not this gen, the next process node isn't that small. From what I understand, the chiplets can either go up slightly to 10 cores at the same size, stay at 8 cores at the same size but slightly less dense to improve thermals, or stay at 8 cores and shrink down a little.
That being said, the IO die will move to 7nm sooner or later which will free up a good chunk of space on the package. You'll still probably get 2 chiplets on a desktop Ryzen, but there's scope to add more chiplets on EPYC and Threadripper or add in something else entirely.
Those slides though still show EPYC Milan at 64 cores though, so I don't think we'll see core count increases in Zen 3. There's no point really; let the reality of 16 core desktop parts, 64 core workstation parts and 64 core server parts sink in before we move to 20 and 80 cores
OS kernel scheduler needs to know rough topology of cores and caches to know relative cost of moving a thread to another core. That is the main reason for patches such as znver3 discussed above.
So I presume then an 8 core CCD, rather than twin 4 core CCXs, would require an update to the scheduler. So if what @Postmodum was reading is correct then Zen 3 would still be twin CCXs, it's just unified L3 cache over the top.
Update isn't necessary, but will be beneficial.
Dwarf Fortress especially will love it
I'm expecting good things.
Jump on the OC3D article I linked, the slides are in there.
