Associate
- Joined
- 30 Dec 2010
- Posts
- 3
Multiple Cores
Hi All,
I'd like to see the guys paper, and he does exist at the University of Glasgow.
I work for a company that have been using FPGA's for quite some time to do MPEG2/MPEG4 Encoding and Decoding (Ericsson TV, I do not represent their thoughts or opinions in anyway and they are all my own
).
Now as to getting a 1000 cores onto an FPGA well as I say I'd like to see the paper he wants to present. From personal experience I've made Barrel Processors that were 'almost' Turing Complete (didn't have Branch capability) that were physically 16 Pipelines yet were logically 192 cores (context switched on every clock). SO if he is taking this approach he may indeed have a 1000 virtual cores with VERY VERY simple pipelines.
It will be interesting to see how he proposes to get information around the cores as this is the bottleneck. Pico Chip had an interesting approach as they would have some very simple cores an interesting muxed data bus that would shuffle data around, the sequencing of the data being shuffled around was generated by the compilation of the original software.
There is an interesting statement about using FPGAs to reduce the power. Weeellllll that isn't exactly true. FPGAs use the very old idea of creating ROM logic, your inputs are the address, the value at the address is what you want to happen. So effectively you have very large arrays of memory which in itself has interesting power considerations. The main problem is that the latest FPGAs are VERY deep submicron and suffer from significant amounts of leakage current so they will just happily 'glow' without doing anything. Also, as I don't need to tell you all here, the faster something is clocked you generate more crowbar current (assuming CMOS ) and if you don't design with Low Power techniques at the RTL stage then you won't be saving any power.
The Statement that an FPGA will run faster than a normal chip (ie an ASIC) is to a certain degree '******'. The issue is that the placement of the 'logical' functions is scattered and you may have some very fast 'logic' however to get the signals back an forth takes approx 60% of the time available because the placement of the 'logic' is like using a scatter gun. A WELL designed ASIC with good layout of the logic will be SIGNIFICANTLY faster because the 'logic' will be fast and the connection to the next logical block will be fast as it's been placed nearby.
So as I say, I will be very interested in this guys paper and when I get hold of it I'll pass it on to you guys here if you are interested.
Oh and by the way the reason why I am here is because I am going to be using my machine (when it arrives) to design a slick low power processor.
Best Regards
Andre'
Hi All,
I'd like to see the guys paper, and he does exist at the University of Glasgow.
I work for a company that have been using FPGA's for quite some time to do MPEG2/MPEG4 Encoding and Decoding (Ericsson TV, I do not represent their thoughts or opinions in anyway and they are all my own
).Now as to getting a 1000 cores onto an FPGA well as I say I'd like to see the paper he wants to present. From personal experience I've made Barrel Processors that were 'almost' Turing Complete (didn't have Branch capability) that were physically 16 Pipelines yet were logically 192 cores (context switched on every clock). SO if he is taking this approach he may indeed have a 1000 virtual cores with VERY VERY simple pipelines.
It will be interesting to see how he proposes to get information around the cores as this is the bottleneck. Pico Chip had an interesting approach as they would have some very simple cores an interesting muxed data bus that would shuffle data around, the sequencing of the data being shuffled around was generated by the compilation of the original software.
There is an interesting statement about using FPGAs to reduce the power. Weeellllll that isn't exactly true. FPGAs use the very old idea of creating ROM logic, your inputs are the address, the value at the address is what you want to happen. So effectively you have very large arrays of memory which in itself has interesting power considerations. The main problem is that the latest FPGAs are VERY deep submicron and suffer from significant amounts of leakage current so they will just happily 'glow' without doing anything. Also, as I don't need to tell you all here, the faster something is clocked you generate more crowbar current (assuming CMOS
) and if you don't design with Low Power techniques at the RTL stage then you won't be saving any power. The Statement that an FPGA will run faster than a normal chip (ie an ASIC) is to a certain degree '******'. The issue is that the placement of the 'logical' functions is scattered and you may have some very fast 'logic' however to get the signals back an forth takes approx 60% of the time available because the placement of the 'logic' is like using a scatter gun. A WELL designed ASIC with good layout of the logic will be SIGNIFICANTLY faster because the 'logic' will be fast and the connection to the next logical block will be fast as it's been placed nearby.
So as I say, I will be very interested in this guys paper and when I get hold of it I'll pass it on to you guys here if you are interested.
Oh and by the way the reason why I am here is because I am going to be using my machine (when it arrives) to design a slick low power processor
.Best Regards
Andre'
