AGESA patch D is out for Asus with release 3003 that came yesterday - however its no better for fclk, it only adds the SAM slider.
G.skill Trident Neo 3800 CL14 issues
- Thread starter OC2000
- Start date
Is there anything you can suggest I do to improve these timings. Its running at 1.5V (XMP Spec) but only getting a Latency of 55. I've seen low 50s with similar timings on other 5000 series. The timings in the image generate 2 errors with D Rams easy memtest, but at 14,14,14,28,40 they pass fine as well as in mem5test.
If it is still happening with 2 sticks then it's most likely fclk related but that doesn't necessarily mean you have a bad chip though, it's more likely that due to the bios being new that things aren't optimised properly yet.
Have a look at some of the weird voltages used to get FCLK running high on this board.
Shouldnt IOD voltage be closer to 50mv below SOC voltage?
SOC 1.1875
IOD 0.70
Correct IOD - ~1.1825
I am using
SOC 1.175
IOD 1.125
Last edited:
tWTRS 3 is the minimum: possible, small benefit in latency
tWTRL 6 is the minimum: doubt you will get this to work, small benefit in latency
tRDRD/tWRWR SCL: 2 minimum but unlikely, 3 should be possible. Small benefit in latency. 2 works on B450, 3 on X570. Motherboard memory trace layout quality dependant.
tWR tCL-4 (10) minimum: possible, small benefit bandwidth and latency
tRCDWR 8 minimum: allows tCWL to go lower
tCWL minimum = tRCDWR. Hard to stabilise at high performance settings below 10. Leave tRDWR and tWRRD at auto while tuning this.
tRTP minimum = 2 x tWTRS.
tRDRDSD/tWRWRSD: only applies to dual rank sticks, set to 1 / 1 for single rank, 4 / 6 for dual rank
tRDRDDD/tWRWRDD: only applies when using 4 sticks. Set to 1 / 1 for two stick configurations.
tRP: tCL - 2 works well in most cases. Very minor effect on latency, used to adjust tRC value.
tRAS 21 minimum: will cause boot failure reading storage when set too low. Scales with voltage, 22 is possible at 1.5v with exceptional single rank sticks, 23 with similar quality dual rank. Allows reduction of tRC.
tRC = tRAS+tRP. Little effect on latency, used to adjust tRFC value.
tRFC = multiple of TRC, scales with voltage. tRFC too low can cause corrupted data to be written to storage - risk of killing an OS. Good effect on bandwidth and latency, particularly evident in memtest run times in ryzen dram calc. Motherboard/bios memory training affects tRFC minimum. Too low: no post, slightly too low: OS corruption risk. Below 230 @ 3800mhz is getting very risky.
Increasing SOC Loadline calibration will help stabilise your vSOC voltage. Ideally you dont want it to dip below its set value. As Guest2 is saying above it has an effect on your vDDG sub voltages so you want the vSOC rail to be as steady as possible and minimum 50mv above your IOD and CCD voltages at all times. You may as well manually set the switching frequency of the SOC phases to the maximum while youre making that change. There's so little power going through the SOC phases when using a CPU without an APU that heat and efficiency penalties normally associated with these changes are negligible.
If you can tune down your SOC, CCD, IOD and CLDO VDDP voltages when you have finished your memory and fabric overclock that can give your cpu some more power budget to boost with. These components form part of the overall package power used to adjust turbo behaviour. Even if you use PBO to override limits you can gain a little extra core speed by minimising these voltages. No effect if using a manual cpu multiplier or per ccx overclocking (PB2 disabled).
tWTRL 6 is the minimum: doubt you will get this to work, small benefit in latency
tRDRD/tWRWR SCL: 2 minimum but unlikely, 3 should be possible. Small benefit in latency. 2 works on B450, 3 on X570. Motherboard memory trace layout quality dependant.
tWR tCL-4 (10) minimum: possible, small benefit bandwidth and latency
tRCDWR 8 minimum: allows tCWL to go lower
tCWL minimum = tRCDWR. Hard to stabilise at high performance settings below 10. Leave tRDWR and tWRRD at auto while tuning this.
tRTP minimum = 2 x tWTRS.
tRDRDSD/tWRWRSD: only applies to dual rank sticks, set to 1 / 1 for single rank, 4 / 6 for dual rank
tRDRDDD/tWRWRDD: only applies when using 4 sticks. Set to 1 / 1 for two stick configurations.
tRP: tCL - 2 works well in most cases. Very minor effect on latency, used to adjust tRC value.
tRAS 21 minimum: will cause boot failure reading storage when set too low. Scales with voltage, 22 is possible at 1.5v with exceptional single rank sticks, 23 with similar quality dual rank. Allows reduction of tRC.
tRC = tRAS+tRP. Little effect on latency, used to adjust tRFC value.
tRFC = multiple of TRC, scales with voltage. tRFC too low can cause corrupted data to be written to storage - risk of killing an OS. Good effect on bandwidth and latency, particularly evident in memtest run times in ryzen dram calc. Motherboard/bios memory training affects tRFC minimum. Too low: no post, slightly too low: OS corruption risk. Below 230 @ 3800mhz is getting very risky.
Increasing SOC Loadline calibration will help stabilise your vSOC voltage. Ideally you dont want it to dip below its set value. As Guest2 is saying above it has an effect on your vDDG sub voltages so you want the vSOC rail to be as steady as possible and minimum 50mv above your IOD and CCD voltages at all times. You may as well manually set the switching frequency of the SOC phases to the maximum while youre making that change. There's so little power going through the SOC phases when using a CPU without an APU that heat and efficiency penalties normally associated with these changes are negligible.
If you can tune down your SOC, CCD, IOD and CLDO VDDP voltages when you have finished your memory and fabric overclock that can give your cpu some more power budget to boost with. These components form part of the overall package power used to adjust turbo behaviour. Even if you use PBO to override limits you can gain a little extra core speed by minimising these voltages. No effect if using a manual cpu multiplier or per ccx overclocking (PB2 disabled).
There is no right or wrong just so long as it doesnt exceed SOC and I think the results speak for themselves.
Thanks for that detailed guide! I will play around with this and see if I can fine tune further.
Will fine tuning this affect the IMC reliability? I've had tuned ram in the passed which degraded the IMC. Im more familiar with graphics cards. This is the first time im looking into overclocking Ryzen properly.
Timings wont degrade an IMC, temperature and voltage can though I guess. You'll be tuning your voltages down from an already safe to use auto setting (1.1v) so there's really no danger there at all, if anything you would be increasing the longevity of your memory controller by reducing current.
Nice timingsI think this is about as good as I can get the ram for benchmarking stable. My new dual rank version of this is now on its way which I’ll tune for 100% stability. Thanks again MrPils for your help and knowledge
Have you stability tested with the Extreme1@anta777 config in TestMem5 v0.12?
Isnt Cinebench R20 primarily for CPU benchmarking, not RAM
What do you get with AIDA64 cache & memory benchmark?
DRAM calc easy & default?
These timings are benchmark stable, but do throw a couple of errors in mem test. At 14 14 14 with the same sub timings they’re fine with no errors. I’d probably need 1.52 to get them stable for every day use which I wouldn’t be comfortable with. Maybe tRC at 39 too.
I’ll get screenshots tomorrow and will be lowering the Soc voltages a bit too.
I’m not keeping these ram sticks though as i want 32gb and 4 sticks are unstable on this system.
I think ram does have an impact on cpu intensive benchmarks especially in timespy. With XMP 3800 CL14 I was getting around 15k in the time spy cpu test. With these timings im getting over 17.5k
Last edited:
The lower 50 timings are on single CCD such as 5600x or 5800x. Going to the 5900x or 5950x is 2CCD and this adds approx 5ns of latency.
Ah, learning a lot today. Thank you. Lowest I’ve seen mine so far is 52.7ns.
Well I barely understand all of this but I think I’m glad I went for the 2 x 16 kit of this ram rather than the 4 x 8.
What’s the best ‘idiots guide’ to sort RAM timings? I’ve learning as I read but everyone has more knowledge and talking about timings with a good understanding so it’s a bit like the toddler observing the professors
What’s the best ‘idiots guide’ to sort RAM timings? I’ve learning as I read but everyone has more knowledge and talking about timings with a good understanding so it’s a bit like the toddler observing the professors
I was like that 2 weeks ago. Reading, watch a video or two and have a play around in programs doing things like reading your memory and looking at timings.Well I barely understand all of this but I think I’m glad I went for the 2 x 16 kit of this ram rather than the 4 x 8.
What’s the best ‘idiots guide’ to sort RAM timings? I’ve learning as I read but everyone has more knowledge and talking about timings with a good understanding so it’s a bit like the toddler observing the professors
Don’t listen to everyone on the internet, they’re not always right or think they know best when really they don’t.
@MrPils has also been a valuable source of information. A RAM sticky would be useful and what programs can be of use, what timings mean and how things may change if the said timings are adjusted
Well I barely understand all of this but I think I’m glad I went for the 2 x 16 kit of this ram rather than the 4 x 8.
What’s the best ‘idiots guide’ to sort RAM timings? I’ve learning as I read but everyone has more knowledge and talking about timings with a good understanding so it’s a bit like the toddler observing the professors
I agree with Guest2 here. Ram timings has always been my weak point. But over the last few days, I've learnt a lot especially from MrPils.
Best thing to do is use the Ryzen DRAM calculator, Set the Rank to Dual, and Dims to 2. and try the safe settings first. Then Fast. Then tighten further using MrPils suggestions in this thread.
To get the exact settings of your RAM for Ryzen Calculator to give you the best timings to start with use Taiphoon to get your ram info. Theres tutorials on this. But basically you want to convert the report to nanoseconds export the complete HTML file and import it into Ryzen DRAM Calculator. Hit Safe settings and input those into BIOS.
Thanks chaps / chapettes
Mrpils certainly seems to be the guru around these parts although I have asked him a few questions already and didn’t want to take the ****!
I have a C8H and the Asus mb runs memory just fine.
Using Samsung Bdie.
Going from 2 x 8 to 4 x 8 required a few changes. I have tried the following and run TM5 20 cycles
3800c14 14 14 14 48 42 1T 4x8. GDM Enabled
3800c14 14 14 14 48 40 2T 4x8. GDM Disabled
tRCDRD may need to be 15/16
The following timings seem to really help getting 4 sticks running.
2 sticks. GDM disabled CR1. . tRDWR / tWRRD. 8 / 1
4 sticks. GDM enabled CR1 . tRDWR / tWRRD 8 / 2
4 sticks. GDM. Disabled CR2 . tRDWR / tWRRD 9 / 3
No difference in voltages running 2 or 4 sticks.
Soc 1.106v LL2 droops to around 1.07v (dmm)
Vddc ccd .975v
Vddg iod 1.0v
Vdimm. 1.48v
ProcODT. 34.3. or. 36.9
Using Samsung Bdie.
Going from 2 x 8 to 4 x 8 required a few changes. I have tried the following and run TM5 20 cycles
3800c14 14 14 14 48 42 1T 4x8. GDM Enabled
3800c14 14 14 14 48 40 2T 4x8. GDM Disabled
tRCDRD may need to be 15/16
The following timings seem to really help getting 4 sticks running.
2 sticks. GDM disabled CR1. . tRDWR / tWRRD. 8 / 1
4 sticks. GDM enabled CR1 . tRDWR / tWRRD 8 / 2
4 sticks. GDM. Disabled CR2 . tRDWR / tWRRD 9 / 3
No difference in voltages running 2 or 4 sticks.
Soc 1.106v LL2 droops to around 1.07v (dmm)
Vddc ccd .975v
Vddg iod 1.0v
Vdimm. 1.48v
ProcODT. 34.3. or. 36.9
I have a C8H and the Asus mb runs memory just fine.
Using Samsung Bdie.
ProcODT. 34.3. or. 36.9
Im hoping to get similar timings as this for daily use once my 2x16GB kit comes. Ill set tRDRDDD/tWRWRDD to 1 though.
Does the ProcODT, Rttxxx do anything for performance or only stability?
Thanks. Ill leave those alone for now. I need to start working on PBO now for single score performance.