Nick's little project

[NickK]

Almost complete - there's some backordered components, some missing components I still need to order and one that jumped off the desk and disappeared (and hour+ of looking and I've not found it - I hear it bound off the keyboard on my lap). I also found a solder short circuit (red arrow) under one of the 330R resistors and sorted that out. I've cleaned up the boards a little but it's currently as much as I can do for now. Also worth noting the right board has a load of components on the under side too.. Probably a good 20 hours of soldering work there..

So back on to the power supplies for the ADC..

 

[NickK]

That’s some tidy looking soldering. What hardware did you use?

A cheap Antex 25W soldering iron. I also used Chipquick TS391SNL lead-free solder paste. You really need to use very little paste when applying direct (no paste mask). The 25W iron is fine for all the small work but has a problem with the larger heat sinking SOT (Q31 and its partner near the red caps). I could have done with a 40W iron at that point.

I have a LED/magnifier lamp that helped massively! Only ~2x or so but that's enough to help. I'm still looking for C16 on the floor...

 

[NickK]

I’d also advise a few pointers on the techniques.
1. Half the amount you think you need then 1/4 it again. I used the green syringe tip and literally a small turtle head of solder. You can always add some at a later date.
2. The paste flux melts being near the iron before the solder melts- beware but don’t panic because it will leap into place but be wary of the components will move.
3. Capillary action is your friend - soldering single corner pins using a small amount *next* to the pin and let it suck it in when it melts. Use this for small pins then switch to drag soldering by only being near the ping on the pad then once both sides of the IC are soldered go across the pins themselves to ensure the bond between the solder and the pin and the solder and the pad are good.

4. Paste will get anywhere - if your right handed, start with the small components - solder right pin (or corners) but rotate the board to fit your solder hand don't try to solder that feels bad or the opposite side of your solder hand.

5. I used normal solder for some components as it blobs better- so through hole works better. Match like paste and solder together.

6. Wash - i used a damp cotton bud with water to give the board a clean and that includes over the solder (wait to cool).

 

[NickK]

ADC update

1. With the protoboard LT3080 power supplies between the ADC and the SMPS
2. With the protoboard digital isolator between the STM32 (and USB) and the ADC thus breaking any ground loops - The isolator board also includes a shunt power supply from 5V to 3.3V.
3. Still using the noisy SDG signal generator for the master clock on the ADC side.

That' noise floor is going south We picked up an additional 27dBV drop!!



And with a 1Khz 1Vrms sine from the SDG:

Yep. Still noisy (no real change)

I've decided enough messing around with PCB (I tried making one but I suck). So I'm going to simply order some prototyping boards - 4 layer for the clock and isolator but just stick with 2 layer for the voltage regulators.

 

[NickK]

So unknown to me I managed to set the upper limit of the spectrums above to 42kHz.

I also thought a bit about the ground loops given the impact that the i2s isolation had - this time on the main power ground reference that comes from one of the SMPS power supplies. Above, there are three possible ground reference points which can result in ground loops - the SMPS ground, the master clock BNC shield to the SDG and the the USB via case touching the USB shield.

I decided to remove the power reference as this has one already via the case - the BNC to the SDG. The result showed an improvement in the sampling accuracy:



So that 100kHz hump is most likely a 100kHz switching fundamental and harmonics and spurs caused by that fundamental switching noise. The sources could be (a) either of the two SMPS bench supplies or (b) the SDG generating the clock.

 

[NickK]

So I've added two 15mF caps (15,000uF) between the SMPS bench supplies and the regulators, it crushed the low frequency noise across the audio spectrum.

So REW also allows you to switch on coherent averaging that suppresses non-harmonic content (ie it's a tuneable filter) for a bit of fun - with 16x sample coherent averaged the noise floor hits -160dBFS



So basically the caps helped both filter the SMPS noise but also combats the power droop caused by the inductance caused by the long leads. (think decoupling cap but for low frequency).

Next up is to finish the clock PCB, make a better non-protoboard set of boards, add some code for the i2C automatic reset of the ADC on clock startup and we're laughing. I'm happy that we're starting to push the limit of the 5572 ADC chip in terms of noise etc. So from that it will be useful with the headphone amp/DAC etc. Once the PCB board is done for the voltage regulators, I can easily change the photo-board regulator to the new RTZ DAC for testing that and the ADC can then provide measurements on that

I'm itching this summer to make a cabinet for a guitar amp build I've talked about and have in the back of my mind.

 

[NickK]

So I've been spending time designing a new clock PCB - this is 4 layer, and is about 100x50mm:


I should be checking and then ordering this PCB (five boards) from a professional prototyping company. This also allows two options for power supply - a LDO or a shunt power supply. The board is now split on both sides - the DC power is on one side and the RF clock generation and filtering is on the underside. The reason for this is so that when the board is secured into place on standoffs, the RF section is clamped between the 4 layer board and the metal chassis to reduce noise.
I could use pulse transformers on the the clock outputs to isolate the external device

I may see if I can squeeze a 4 layer version of the digital isolator board too on the other side of a 100x100mm order.

 

[NickK]

PCBs arrived from JCLPCB earlier in the week - I designed both the isolator and the clock into a 100x100mm 4 layer PCB so they can be cut down the centre and then mounted on standoffs above each other. The clock PCB has and edge gap to make a shielding box for the clock at a later date (that's the silver border around the PCB). Minimum quantity is 5 so I have some spare for other projects at a later date:



The 4 layer PCBs are not much more than 2 layer PCBs now (for the cost of shipping you may as well go for 4 layer). The benefit of 4 payer is simple - noise reduction. It means I can route the fast noise radiating tracks between two ground layers which helps return currents and that in-turn helps reduce the RF noise generated.

I soldered up some components that I had already - ignoring the shunt power supply that I need components for but used the 3.3Vdc from the SMPS bench supply. I'm not risking the CCHD oscillator until I'm happy I'm not going to see big reflections etc so I hooked up the SDG to the PCB pad that would be the output of the CCHD and set it to 2V at 24.576MHz. The idea is to test the signal and the calculate if there's any need for resistors to terminate (match the impedances):



The small (scale) signal is the input from the signal generator. The large is the output signal from my board (again scale is the reason) to test the 1-to-3 fan out chip (signal in and three copies are then output - each buffered and independent).

This has shown I need some 50R resistors to reduce the scale of the voltage reflections. I put some 301R resistors in there just to see if my calculations were correct but I'm not sure they are. So the default is simply swap for 50R resistors in. This means the signal will not have the reflection and thus will not be too large. This is the reason the SDG input is only 2V but the scope reads higher is due to the impedance mismatch. The SDG output impedance is set to 50R to simulate the CCHD output impedance. The mismatch shows how the impedance difference can damage components. However I'm very pleased with the shape of the signal so far - it's perfect.
Once the 50R terminating resistors are in, that should drop the size of the input and the output to 3.3V. Note - you can see the capacitance of the oscilloscope probe on the smaller one - that's why it's got a shallower edge slope. The output doesn't use a scope probe and simply goes output -> SMB -> BNC75 cable -> 50R terminator and scope hence it's 1X and the sharpness of the signal.

I've also moved over the digital isolator ICs from the protoboards to the isolator PCB but I need to test that too but all looking good so far. I hope tonight to then put in an order for the weekend. That will also include the AC mains power supply so the system should be self contained at last. The toroidal transformer is only 7VA and it's will be titchy (only about 250mA at 15Vac so should give me around 20Vdc to play with). The issue I have now is that the regulator heat sinks are a little large to fit - I may get some smaller ones as I don't think they heat up too much.

I've been advised that I can use a £70 TinySA (RF spectrum analyser) to test for reflections better than my scope (also help spot RF noise better). So that may be an option at a later date.

Have to say I'm happy at the progress, so I'm looking forward to seeing the clock running the ADC and it running off the mains power.

 

[NickK]

It is crazy just how much difference ground routing, etc. can be - I was playing around just messing with different layouts, etc. and the difference in noise floor from some fairly small tweaks could be huge. I mostly use the non-plus version of ExpressPCB though so 4 layer isn't really an option (neither do I really know much about best practises with 4 layer).

I assembled all the components so far - that's the clock and the isolator boards in the ADC however at the moment the clock fan output isn't high enough to trigger the ADC to start clocking. I have a parallel 49.9R terminator at the the load end, and the source output of the fan out chip is 45R so in theory it should be a perfect wave but 1/2 the output voltage (1.5Vpp) which is annoying because doing the same with the SDG load generator gives a 3.3Vpp. This makes me think that I should simply remove the 49.9R resistor (or change for a higher) to increase the voltage swing.

So far I've been lucky with the assembly:
a) soldered the fan out chip the wrong way around when I used the SDG - chip still works
b) can simply use a short across the enable pin (no 100K resistor I had planned).

so I'm hoping that I can get away without a terminating resistor

 

[NickK]

Yes - I have a 301R source parallel resistor in there now. I need to verify that the timing coming out is 50:50 duty cycle (due to difference in slopes etc) but I got the clock (using the oscillator) and the isolators working at lunch time today:



Not bad at all - considering this (a) isn't using the 15,000uF caps on the input (improves low frequency), (b) not using the 5.0-3.3V shunts but using the 3.3V supply SMPS. That should also reduce the noise that the clock is subjected to (resulting in jitter).

 

[NickK]

Added the 15mF caps (but 3.3V still without low noise regulated from the SMPS). So this is once it's warmed up and stabilised. Looking better.. will try with a 15mF on the 3.3Vdc tonight and see if that can drop further (all also help clearing up the mess of cables too).




I should say that the red line - the peak - is really set by two things:
1. ADC design - this is noise coming from the ADC itself. The 5572 is stated as about 112 dB dynamic range. The THD+N 122-124dB. This means you can see the red line peaks out at about 120dB noise floor. Once a signal is introduced (1KHz) the ADC is starting to show its noise in operation (also the SDG signal generator itself isn't quiet). The slopes at either end are noise shaping from the ADC design - that includes the peak of noise reshaped to 50KHz+. That will always be there.
2. spurious noise in the case but this seems to be minimised (I still have a little more to go to minimise) but power supplies are a key contributor.

The white line is a rolling 16 average - so this is the average noise, not the peak, which is a good indication of power supply noise. If you imagine a scale of minimum and maximum with the average in the middle, the quieter the power supply and design, the less range between minimum and maximum so thus, the average will decrease. I suspect that 160-170dB is the minimum base and the rest is noise contribution.

When you're doing testing - you're not sampling a massively dynamic sound like a song but instead you're sampling a static tone - that tone really means we can use the peak (ie looking for noise) but the main thing is using the average to see the frequency response between input and output of the component under test.

It should also be clear after this exercise - including replacing the clock with a low close in jitter quiet clock, does make a difference but the largest difference is to reduce the noise by digital isolation (ie have a galvanic isolator on the i2s line) and having very quiet power supplies and design. I got a 27dB drop in noise from the isolation, the power supplies really make the backbone of the noise - that noise then reduces jitter (which at this stage is less than you can hear) and finally a polish is the CCHD oscillator which really by itself isn't going todo much until your clocking is that bad in the first place .. the fact that it can be ultra quiet with very low noise power supplies (shunts) means it will help overall but you're back to the power supply noise being the largest contributor to sound quality.

Here's the difference between the two clocks (left new CCHD clock, right old SDG generated master clock) with the same SDG generated 1KHz tone:


If you look carefully there is small differences in the noise and the skirt. Other than that.. not much except that the new clock is less noisy.

 

[NickK]

50Hz spike due to interference from the mains supply?

Yes - most likely through the 3.3V rail as that was provided direct through the SMPS bench supply and not through the regulators. Also the box is right next to the 8 way mains block at the moment with the cables a mess around it (the regulators are outside of the box bare too at the moment as well that doesn't help). Long power cables become receiving antenna for any noise around. That same noise source is probably causing the other spikes. The noise spike on the 1KHz is most likely the same source or possibly on the cables to the SDG.

Voltage regulators add PSRR (power supply ripple rejection) usually between DC and 100KHz so the 3080 voltage regulators drop that by a good 60dB. The onboard 5V to 3.3V supplies should drop that even further (a good 90dB). The best voltage regulators only offer PSSR to about 1MHz so any noise above that (in or out from components) has to use ferrites (ie CLC filters). I have some but not all installed and I may change the values on some for better noise reduction.

For reference the signal strength we're seeing here is:
0dBV is 1 Volt RMS (1000mV RMS)
-120dBV = 0.001mV RMS (0.000001 VRMS)
-140dBV = 0.0001mV RMS
-160dBV = 0.00001mV RMS (1e-8 VRMS).
The SMPS supplies are rated as (at best) 120mV peak-to-peak of ripple on the output - that would show up as 50 or 100Hz under the switching noise. So to get from 120mVpp or other received noise on the cables, we need to filter out that noise (PSRR).

So although the ADC (and most ADCs) can't get below 130dB realistically, You want the averaging to have as low noise as possible to allow differentiation between measurement noise and device noise. Hence the focus on getting to about -140dBV or below for the average noise. Essentially makes the measurements more 'reliable' as they're not prone to noise. The devices I will be measuring may not get below -120dB and in the case of tube amps probably not below about -80dB (so a warning to all you digital 24bit freaks that use tube amps or CD players with tubes in the output stages!). The dynamic range of the ADC will mean you will only see that range below the largest peak.. hence the average higher noise floor in the 1KHz tone.

The next step I will do this weekend to finalise the BOM for the next order. I've now removed the SDG from the system, the next stage is to remove the SMPS supplies completely (although they do provide 120mV ripple supplies and filtering themselves so I may need to add more filtering to my supply in future).
The power supply I have planned is a linear supply:

Mains AC --240Vac--> Schaffner IEC mains filter (includes fuses and common mode choke filtering, PSRR) --240Vac--> Switch --> mini torrid (7VA) --2x15Vac-->. (at this point I hope for about 120mV or better ripple)

Then two of these:
--15Vac--> full bridge rectifier --20-22V Vdc--> CLC (15mF cap, PSRR) --20Vdc-->

Into the voltage regulators (I have one 3080 each for +15V, -15V and +5V)
--18-20Vdc--> Voltage regulator (PSRR) --2x15Vdc, 1x5Vdc-->

These then go to the ADC (it has it's own regulators that add further PSRR) plus the ADC itself has PSRR built in. The 5V line then goes to the clock board (with a inboard 5V-3.3V power supply) and the isolator that also has it's own 5V-3.3V power supply.

The important point is that the clock and isolator boards actually prevent noise from the those boards from travelling up the 5V line that supplies the ADC too. I know at the moment that they do inject some noise as I can see the scope trace is note entirely flat - this currently goes to the SMPS 3.3V.
The clock board has a chain of ferrites to block in and out going noise but I may have to change the lower impedance ferrites to something with a bit more bite (impedance) to drop that noise more. As the noise is is >1MHz the voltage regulators don't have any PSRR at this range. I may add a ferrite to the 5V regulator. Although the 5V regulator is only used for digital - you don't want the clocking or the logic voltage noise to cause false triggering - hence the focus on this. Also you don't want that noise getting into the +15V and -15V supplies as they are supplying the analogue measurement front ends!

In the end I will probably design a 2 layer PCB to replace the protoboard regulator board I have and the power supply board into smaller PCBs. As you order 5pcbs for each that means I have them for other projects too.

 

[NickK]

Next up - the guitar tube amp.. basically a JCM800 front end but only a 2 watt backend:

This should rock in a cab with a 12" speaker. It should get to about 100dB but I will add a attenuator inbuilt.

 

[NickK]

Little update in that there's not much - I've had to sort out other projects (including remortgaging, laying garden paths, family visits etc).

I have been looking at the wood work in the interim. The size initially is 705x478x275 which is perhaps too large for a 1x12. I've been looking at other cab sizes, for example some Zilla cabs (ignoring they're not combos) - 620x490x280, 620x470x360 and some Marshall cabs/combos 610x535x230, 510x490x245, 620x490x252 (combo), 500x406x245 (combo valve 10" speaker).

So I'm thinking that a possible reduction in width to 620mm, throw away the golden ratio and then simply look at making it a 620x490x278. The ply I have is 12mm, so I will double it up because I want to be able to sit on it (and it's not going anywhere on a regular basis).

 

[NickK]

Well the Mrs' mum is pending a more detailed diagnosis and so she's intending to take a sabbatical to assist, so saving some pennies for the time being - the amp is not dead just will need to take a back burner I have the wood so I may continue with that in the interim to keep me busy.

I did an experiment on the A220 at the weekend - specifically looking at the power supply performance across the frequency range and the noise level. Basically I used 8R 100W dummy loads, put the signal generator (both outputs synchronised) and then used the scope Bode plot to run across a frequency response. Then I measured the response of both the pre-amp opamps and the power supply for the pre-amp opamp.

In the past I changed the caps used in that pre-amp power supply, upping the capacitance a little but also dropping the ESR to about 5mOhm according to the capacitor specs (low ESR in parallel). The result means the existing power supply provides a better power response but it's still using the same old technology (it has a regulator but it's a simple design so suffers from a few issues).

Two points - the opamp pre frequency response is good, the noise level is about 60-80dB which means the opamp power supply sucks. Measuring the power supply for the opamp, you can see the volume has an impact on the frequency response of the opamp - that is not desirable as it means the sounds varies depending on volume (irrespective of the class A/A2 transition). So in short that power supply response should be flat. It says that the power supply main power banks are too small for higher volumes and that even smaller volume changes cause a difference in frequency response driven by the power supply. Being flat means that the power supply should/needs to have a low impedance across the power supply range and the power should be as quiet as a mouse for the opamp on the front to perform to it's best.

In the past I've designed a very very low noise power supply for the ADC (in this thread), so the temptation is to take that design and apply that to the opamp itself. This means bypassing the old pre-power supply, replacing that by a regulated shunt power supply which then results in a very low impedance for power.. (ie it can get current at high speed and low sustained current with equal ease) and the power will be ultra low noise.
Todo that I'm tempted to replace the opamp and simply build a pre-amp opamp board (perhaps using a better singles/dual ICs) then building the power directly on that board with caps etc. I'd also add space for the decoupling film caps that are current floating and then simply use shielded wire to connect. Perhaps on a 100x100mm board so I can get it on the size for prototype PCB orders. If I do the pads correctly, I may be able to support a number of different opamps
That would keep me busy whilst not costing the earth (the tube amp would be quite expensive).