GA-EX58-UD5 BIOS F1O UPDATE

OLDPHART

OLDPHART

OLDPHART

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Flashed my Bios with F10, reset my 4.0GB profile, ran Intelburntest on high 10 runs / threads 8 passed as a check for stability. Burned a few disc's, gamed , etc, every thing seems ok.

Noticed a couple of new Bios settings -
1. channel interleaving--6--(auto)
2. rank interleaving---4---(auto)
3 dynamic vcore(DVID)---(auto)

To enable DVID > you need to use normal mode within cpu vcore.

Can some one help me on these settings, as l have not come across these before.

Cheers OLDPHART.
 
With DVID, couple of things you need to start with.

  1. Vcore needed for your 100% loaded stable clock.
  2. Your cpu's default voltage, differs from chip to chip.

To get the first one check cpu-z under 100% load, use prime or linx etc. The second one is a little more involved, set the multi lower in the bios, way down (default cpu speeds). Set the vcore to normal. Reboot into windows, again check the actual vcore under load.

Now back in the bios (obviously put the multi back), leave/set the vcore to normal. In the advance settings set the DVID offset number to the difference between the overclock vcore and the default vcore.

e.g. on a 4Ghz clock D0. 1.2625-1.2125=0.05v

Now go and check the 100% load value in windows is the same as the original overclock value. You could also try using the default Vcore displayed in the bios, but of course that takes no account of the vdrop+vdroop. Should work though (just note, default Vcore in bios can change with turbo mode on/off). You should now see the vcore changing with the load and drop even lower with speedstep.

Some other settings that seems to be successful with it. LLC enabled, disable C1E (stops MB buzzing apparently), enable all other energy features, "C3/C6/C7 State Support" etc. Power management profile within Windows set to high performance.
 
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Channel Interleave: Higher values divide memory blocks and spread contiguous portions of data across interleaved channels, thereby increasing potential read bandwidth as requests for data can be made to all interleaved channels in an overlapped manner. For benchmarking purposes when using three memory modules, a 4-way interleave may surpass the scoring performance of setting 6-way interleave depending on the benchmark and operating system used (32-bit vs. 64-bit). We did find however that a 6-way interleave was capable of a higher overall BCLK for Super PI 32M than using a 4-way interleave setting (unless of course you run single- or dual-channel and appropriate channel interleaving thus decreasing load upon the memory controller).

Rank Interleave: Interleaves physical ranks of memory so that a rank can be accessed while another is being refreshed. Performance gains again depend on the benchmark in question. For 24/7 systems using triple-channel memory configurations there is no advantage to setting this value below 4 while Channel Interleave should be left at 6 for best overall system performance.

Taken from XS
 
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