Associate
Thumbs up from Tech Jesus, nuff said.
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AMD demonstrates Ryzen 9 5900X prototype with 3D V-Cache stack chiplet design
- Thread starter RavenXXX2
- Start date
Soldato
They're not even a thing yet so it's a bit premature. I would very much doubt any changes are required, it's still Vermeer at the end of the day. Might need a BIOS or microcode update to get the extra cache addressable.
Associate
Yup, good enough for me! Wondering when this might be a part of a released product?
Soldato
We've not missed a generation, Threadripper isn't usually out until 6 months after desktop Ryzen. it's just a little late this time, and there's a boat load of EPYC orders to fill before Threadripper starts eating up multiple chiplets.
Soldato
Next year. Lisa Su said herself this is going into production end of this year, so don't expect anything before Q1 next year.
Soldato
Timings on DDR5 are horrendous.
I was going to get a 5800x to upgrade my 3600, think I'll wait and grab the 5900x(t) or whatever they are going to call it, instead. That'll do me for a few years.
I was going to get a 5800x to upgrade my 3600, think I'll wait and grab the 5900x(t) or whatever they are going to call it, instead. That'll do me for a few years.
Don't forget these timing are the standard JEDEC timings, XMP 3.0 hasn't arrived yet.
Soldato
- Joined
- 18 Mar 2010
- Posts
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What do you mean by this?
Don
https://www.anandtech.com/show/16143/insights-into-ddr5-subtimings-and-latencies
e.g. JEDEC standard for DDR5-3200 is CL22 at best, CL28 at worst
vs JEDEC DDR4-3200, CL20-CL24
latency goes up massively as you move through the speed grades
e.g. >16.67ns latency on almost every "average" bin DDR5, vs ~14ns for DDR4, 13-14ns for DDR3
Caporegime
With timings like that i can't see DDR5 being any better than DDR4, the timings are just as important, for ANY CPU. It might be better for iGPU's with a higher bandwidth but that's really it.
Soldato
Bearing in mind these are just JEDEC, which means almost nothing to us enthusiasts who will go for tuned. We also don't know how well the IMC will cope with it yet.
What's also interesting is two channels per DIMM, lower voltage, voltage/power reg on the RAM itself and a massive leap in density.
What's also interesting is two channels per DIMM, lower voltage, voltage/power reg on the RAM itself and a massive leap in density.
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Yeah I think people are jumping the gun on DDR5 and we'll likely see a change in perception once the enthusiast kits arrive.
for about a week.
Caporegime
1.5v? You people are nuts.