AMD Zen 6 rumours

[Grim5]

AMD Zen 6 Rumored to Match Nova Lake With Up to 288MB Cache

New rumors suggest that AMD is preparing a much more aggressive cache configuration for its upcoming Zen 6 desktop processors, directly targeting Intel’s next-generation Nova Lake platform.

www.guru3d.com

Zen 6 rumoured to have big gains in cache to match with Nova lake leaks.

1 CCD = 144MB
2 CCD = 288MB

How much extra advantage this will have for gaming, who knows.

Minimal most likely

 

[Capitano]

Minimal most likely

Its going to be more than just "minimal" but I cant see a crazy jump. I would suspect its diminishing gains after 96mb or so

 

[Rob_B]

HUB did a video on cores vs cache but using Intel, regardless I think it'd be due an update in this circumstance.
I guess we need to understand what fits in the 96MB/144MB cache, I can't say I'd know exactly what the limit would be, just 'how much' game logic for instance is there?

 

[michty_me]

Is it nt also jumping from 4nm to 2nm?

 

[mark 11:11]

id gues for certain [and probably very specific and potentially niche] use cases the dual ccd with loads of cache might have a major major major bonus in
i mean i think thats a bit too far for my example but im moving over to a 7800x3d from a 5900x shortly and i think for my music production work to some small degree
the added cache might very well help with certain vsts and certain other parts of the daw but i doubt in my case it would really then scale to a dual ccd with 24 cores all being fed with
huge amounts of cache or whatever
but id imagine there are other certain use cases

 

[Rroff]

Minimal most likely

The advantages of X3D aren't just about amount of cache but how you can distribute cached instructions and so on and beyond my knowledge but there is likely also a balance against lookup of cached data and as the size of the cache gets bigger you increase the access latency.

Just indiscriminately throwing lots of L3 cache at Intel CPUs alone likely wouldn't result in a big increase in gaming performance.

 

[humbug]

The advantages of X3D aren't just about amount of cache but how you can distribute cached instructions and so on and beyond my knowledge but there is likely also a balance against lookup of cached data and as the size of the cache gets bigger you increase the access latency.

Just indiscriminately throwing lots of L3 cache at Intel CPUs alone likely wouldn't result in a big increase in gaming performance.

This....

Intel already had a CPU with extra cache, see video below, they abandoned it because it did very little and nothing for discreet GPU gaming.

Just increasing the amount of cache on its own is not going to help, it might even make it worse as a larger cache pool = increased latency, you have to build in tech to overcome that latency, something AMD have got very good at over the years due to their chiplet design having a high latency, you also need to have a very good branch predictor to make use of that larger memory pool, if your branch predictor is more miss than hit in the large cache pool then its not going to help.

Having a larger cache also make the physical surface area of the cache larger, so fetch takes longer, L1 is much faster than L2 which is much faster than L3 in part because its A, closer to the core and B, smaller, AMD stack their extended L3 on top of; or these days underneath the integrated existing L3 cache, a vertical path to that cache is much faster than a horizontal one.

You can't just slap some more cache on it and call it good, it doesn't work like that. AMD's extended cache works because of the engineering they built around it to make it work.

 

[Capitano]

This....

Intel already had a CPU with extra cache, see video below, they abandoned it because it did very little and nothing for discreet GPU gaming.

Just increasing the amount of cache on its own is not going to help, it might even make it worse as a larger cache pool = increased latency, you have to build in tech to overcome that latency, something AMD have got very good at over the years due to their chiplet design having a high latency, you also need to have a very good branch predictor to make use of that larger memory pool, if your branch predictor is more miss than hit in the large cache pool then its not going to help.

Having a larger cache also make the physical surface area of the cache larger, so fetch takes longer, L1 is much faster than L2 which is much faster than L3 in part because its A, closer to the core and B, smaller, AMD stack their extended L3 on top of; or these days underneath the integrated existing L3 cache, a vertical path to that cache is much faster than a horizontal one.

You can't just slap some more cache on it and call it good, it doesn't work like that. AMD's extended cache works because of the engineering they built around it to make it work.

Pretty spot on, AMD have done a stellar job in that regard which is why I think the rumoured increase in cache size will actually make a reasonable difference. If it makes no or very little difference, I doubt they even bother with increasing it in the first place.

Zen6 shaping up to be pretty spectacular if the rumours are all true

 

[Grim5]

AMD has announced specs for its next gen AI machines that use Zen 6 CPUs

In the announcement AMD confirms that Zen 6 CPUs have 12 cores per CCD. Zen 6 CPUs are also built on TSMC 2nm

AMD CEO Shows Off Worlds First 2nm Chips For Next-Gen Helios AI Rack: Venice "Zen 6" CPU & Instinct MI455X GPU

AMD has shown off its next-gen and the world's first 2nm EPYC Venice "Zen 6" CPU & Instinct MI455X, designed for Helios AI Racks.

wccftech.com

 

[Capitano]

AMD has announced specs for its next gen AI machines that use Zen 6 CPUs

In the announcement AMD confirms that Zen 6 CPUs have 12 cores per CCD. Zen 6 CPUs are also built on TSMC 2nm

AMD CEO Shows Off Worlds First 2nm Chips For Next-Gen Helios AI Rack: Venice "Zen 6" CPU & Instinct MI455X GPU

AMD has shown off its next-gen and the world's first 2nm EPYC Venice "Zen 6" CPU & Instinct MI455X, designed for Helios AI Racks.

wccftech.com

Rumours were correct then! the 12 core CCD's are going to be a game changer

 

[doodah]

Drool activated......

Each AMD EPYC Venice "Zen 6" CPU comes with up to 256 cores based on the Zen 6C architecture, and each Instinct MI455X GPU packs several thousand compute units. The Helios rack scales up to 2.9 Exaflops of AI compute, 31 TB of HBM4 memory, 43 TB/s of scale-out bandwidth, and up to 4600 CPU + 18,000 GPU cores.