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7nm Process - Game changer?

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How far does your signal propagate during a clock cycle at that kind of frequency? Not far at all! Fractions of current die sizes. You will have some interesting challenges keeping bits synchronised.

The thing is that even an increase to frequencies of 10-15 GHz, would still be a pretty significant improvement!
 
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The thing is that even an increase to frequencies of 10-15 GHz, would still be a pretty significant improvement!

I think Dave was getting at the issue of the path delays being a dominant factor in the frequency of the ICs. So, great, you've got a flip-flop (single bit store element) that works at 10GHz, but can the signals (electrons or lack thereof) wobble their way down the routing between flip-flops between clock edges?

At 10GHz, your time between clock edges is 100ps. The speed of light is 300,000,000m/s in a vacuum, where the wavefront of an electronic signal in silicon propagates at about half the velocity of a vacuum [requires citation]. So that's 150,000,000m/s * 100ps, giving 15mm!

The problem is, this is one of many factors that add up to your propagation delay. You've got the delay of your combination logic (the stuff doing the actual "maths" between flip-flops), and the parasitic capacitance that need to be charged before your signal reaches your gate thresholds. Also, you have a setup and hold delay to meet, which is the time before the clock edge that the signal has to be stable.

So lets assume you can (if you're lucky) get your signal down a 5mm path before the next valid clock edge. 5mm is quite difficult to glue cores, caches, IMCs, etc together. Also keep in mind the routing is never as the crow flies, and can be quite convoluted.

Anyways, really dodgy maths, but it is the rough idea.
 
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So lets assume you can (if you're lucky) get your signal down a 5mm path before the next valid clock edge.

https://www.sciencedaily.com/releases/2017/11/171129120254.htm
Interesting follow up article which gives a bit more detail. The picture of carbon transistors is especially geek eye candy worthy.

I definitely don't understand the science at play here so I am not going to postulate anything other than it looks like transistor density could be orders of magnitude higher than current technologies so along with the speed increase we could see vastly smaller SoC devices where 5mm would be a significantly large distance.

I also found the financial implications of 7nm vs 10nm very interesting and a very solid reason for modular design on ryzen and the nextgen GPU's as well as interesting in terms of the gamble incurred by AMD in jumping 10nm tech.

Thanks for digging up and sharing the articles.
 
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I also found the financial implications of 7nm vs 10nm very interesting and a very solid reason for modular design on ryzen and the nextgen GPU's as well as interesting in terms of the gamble incurred by AMD in jumping 10nm tech.

There is no gambling at all from AMD - AMD works with IBM, GloFo and Samsung and with these, the 10nm is a half-node shrink, no need to do anything on it.
7nm is a full-node shrink from 14/12nm.
 
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Quantum entanglement or a better description would be Electron teleportation

https://futurism.com/teleportation-could-possible-using-quantum-physics/

It's certainly a long way off but if we can eliminate the distance to move an electron by teleporting it instantly then it open doors to pretty much unlimited processing power

The current consensus is that QE doesnt allow information to propogate faster than the speed of light so this doesn't really resolve the issue that 0h no not again quite eloquently highlighted
 
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