http://videocardz.com/52874/hynix-high-bandwidth-memory-presentation-leaks-out
tags like I've done for you above - Rilot
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Hynix HBM Presentation - many slides!
- Thread starter Orangey
- Start date
http://videocardz.com/52874/hynix-high-bandwidth-memory-presentation-leaks-out
Soldato
Just seen this, going to read it later.
Soldato
HBM + 20nm, yeah boi !
My next card.
My next card.
Associate
Interesting, thanks! 
Caporegime
Soon enough we might get some slides written in plain English.
Can anyone make any sense of anything in these slides?
Can anyone make any sense of anything in these slides?
Soldato
Soon enough we might get some slides written in plain English.
Can anyone make any sense of anything in these slides?
I read it as first gen HBM for GPU's will come in 4GB flavors and be much higher speed / lower power than current GDDR5, and replace it altogether going forward.
Later revisions of HBM will be 8GB+ on GPU's and sky's the limit in other areas that HBM can be used.
This is the future, looking forward to it.
Caporegime
- Joined
- 18 Oct 2002
- Posts
- 33,188
no.
grrr, this is really simple stuff and most of the relevant slides are exceptionally straight forward.
First gen starts with
1 stack = 2 or 4 hi, meaning 2 or 4 chips per stack. Initially these are 2Gb per chip(note the small b, that is 256MB per chip) meaning up to 1GB per stack.
Each stack has a 1024 IO(meaning 1024 lanes between the stack and gpu), each stack is 128bit and offers 128GB/s with chips clocked at 1Ghz(low clocked for power, low voltage and because temps of the bottom chip will be a factor).
The second generation increases this to 4 or 8 chips, and the chips being 8Gb(again small b, so 1GB per chip) meaning 4 or 8GB per stack. It also increases per pin speed from 1Gb/s to 2Gb/s(going from 1 to 2Ghz basically).
Per stack has nothing at all to do with per gpu, it's going to be how many and what density they want to use.
Remember those are generations with big changes, the density is set to increase within a generation. IE the first gen chips will have 1GB stacks and almost certainly 2GB stacks very soon, but still at first gen speeds. We won't see 8 hi stacks or 2Ghz speeds on the chips till the second generation. When we get 2GB per stack in the first generation is unknown at this point.
I'm not at all convinced that the 390X will come with HBM yet and isn't just a rumour, but we are very close to HBM being financially viable so it's possible.
So lets say the 390X has a 512bit bus, it can have 4 stacks of HBM, each stack will be 1GB(potentially 2GB), each stack gives 128GB/s, meaning 4 or 8GB with 512GB/s.
It might be a 384bit bus with 3 stacks(3 or 6GB) giving 384GB/s of bandwidth. It will be more comparable to Tonga bandwidth efficiency than Hawaii but HBM won't be directly comparable, the other slides talk about effectively being able to send more commands at a time to a stack and thus have it wasting less time waiting to execute the next command, so it will be more efficient per GB/s than we currently have.
There is also a sensible limit to how many stacks can be used, each extra chip reduces yields significantly so putting 8 stacks on at 1GB a stack is just not going to happen any time soon. I'd say best case scenario is 4 stacks 2GB a stack. I wouldn't bet against seeing 6GB in 3 stacks on a 390X.
grrr, this is really simple stuff and most of the relevant slides are exceptionally straight forward.
First gen starts with
1 stack = 2 or 4 hi, meaning 2 or 4 chips per stack. Initially these are 2Gb per chip(note the small b, that is 256MB per chip) meaning up to 1GB per stack.
Each stack has a 1024 IO(meaning 1024 lanes between the stack and gpu), each stack is 128bit and offers 128GB/s with chips clocked at 1Ghz(low clocked for power, low voltage and because temps of the bottom chip will be a factor).
The second generation increases this to 4 or 8 chips, and the chips being 8Gb(again small b, so 1GB per chip) meaning 4 or 8GB per stack. It also increases per pin speed from 1Gb/s to 2Gb/s(going from 1 to 2Ghz basically).
Per stack has nothing at all to do with per gpu, it's going to be how many and what density they want to use.
Remember those are generations with big changes, the density is set to increase within a generation. IE the first gen chips will have 1GB stacks and almost certainly 2GB stacks very soon, but still at first gen speeds. We won't see 8 hi stacks or 2Ghz speeds on the chips till the second generation. When we get 2GB per stack in the first generation is unknown at this point.
I'm not at all convinced that the 390X will come with HBM yet and isn't just a rumour, but we are very close to HBM being financially viable so it's possible.
So lets say the 390X has a 512bit bus, it can have 4 stacks of HBM, each stack will be 1GB(potentially 2GB), each stack gives 128GB/s, meaning 4 or 8GB with 512GB/s.
It might be a 384bit bus with 3 stacks(3 or 6GB) giving 384GB/s of bandwidth. It will be more comparable to Tonga bandwidth efficiency than Hawaii but HBM won't be directly comparable, the other slides talk about effectively being able to send more commands at a time to a stack and thus have it wasting less time waiting to execute the next command, so it will be more efficient per GB/s than we currently have.
There is also a sensible limit to how many stacks can be used, each extra chip reduces yields significantly so putting 8 stacks on at 1GB a stack is just not going to happen any time soon. I'd say best case scenario is 4 stacks 2GB a stack. I wouldn't bet against seeing 6GB in 3 stacks on a 390X.
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Soldato
Thanks Professor.
Hopefully HBM + 20nm from the get go, if AMD can pull this off will be my next card for sure.
I wonder how the balancing act works between secrecy and marketing. If AMD have this tech ready to go in their next chip they could even get on the evening news maybe. But then Nvidia get extra time to find a partner (like Hynix), rush through a design and start talking about their HBM card. Everyone always says "if they had this they'd be shouting from the rooftops about it", but is it that simple?
Caporegime
Did you not get the message?
Hynix is using AMD's IP in HBM, its a partnership development. i'm sure that comes with some caveats.... something along the lines of "Me first and them later, much later...."
@ Drunkenmaster... thanks
Soldato
HBM 3D Stacked Memory is up to 9X Faster Than GDDR5 – Coming With 20nm AMD R9 390X and 380X Pirate Islands in Early 2015
Go AMD !
20nm + HBM, that's what I wanted to see !
Read more: http://wccftech.com/hbm-3d-stacked-...2015-brings-9x-bandwidth-gddr5/#ixzz3Eph5qFAE
Go AMD !
20nm + HBM, that's what I wanted to see !
Read more: http://wccftech.com/hbm-3d-stacked-...2015-brings-9x-bandwidth-gddr5/#ixzz3Eph5qFAE
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Soldato
Future is AMD
Look forward to 20mn even more.
Look forward to 20mn even more.
Soldato
So from those same set of leaked slides wccftech can say its coming with 20nm in early 2015, don't you just love internet journalism.
Hey man don't shatter the dream. I've been waiting yeeeeeeeeeaaaaaaarrrrs for 20nm, and it's finally happening
Soldato
Looks like my educated guess might have been educated after all. How many people do you think will be selling their 980/970's?
Yeah the same people that are now enjoying 970's/980's will likely move on to better stuff next year, don't think about it to much and enjoy the latest stuff, it's the people that don't upgrade so often that seem to get bent out of shape between each release
Looking forward to this, AMD bringing the pain hopefully, probably about 5-6 months away so plenty of time to enjoy the 980
Yeah the same people that are now enjoying 970's/980's will likely move on to better stuff next year, don't think about it to much and enjoy the latest stuff, it's the people that don't upgrade so often that seem to get bent out of shape between each release
Looking forward to this, AMD bringing the pain hopefully, probably about 5-6 months away so plenty of time to enjoy the 980
4870,5850,670,290. I think I upgrade quite often but maybe not compared to some.
Usually look for a decent increase though.