Caporegime
This is quite an old article now, March this year, but one that seems to have passed us by.
https://www.tomshardware.com/news/amd-3d-memory-stacking-dram,38838.html
One of the problems with 3D Stacking is interconnect bandwidth when passing data outside of the source silicon.
For example AMD's Zen and Zen+ CPU architecture is a half step to separating dies, they are monolithic in that they contain the core and uncore in a single package and split into two zones with a fabric link in the middle joining not just the two halves but an infinite loop of external monolithic dies, "Infinity Fabric"
Zen 2 is a full separation of the core and uncore.
The outer chiplets, which are 7nm, contain the cores and Caches. The central chip, which is 14nm, contains the PCIe lanes, the Memory Controllers, the IO.... and critically the Interconnect Controller IP.
This is the missing technology for true 3D Stacking, by true i'm talking about connecting stacked separate components directly to where it is needed through the component as if it was a 'vertical' piece of silicon. Like HBM.
Not just stacking components and passing data around the outside, Intel.
So you can Stack HBM on top of a GPU which is stacked on top of Core Chiplets which are stacked ontop of an IO die.
Or HBM stacked on top of GPU's, System Ram Stacked on an IO die tapping directly into the controllers.
This saves space, makes the chips overall cheaper to manufacture, increases power efficiency and performance.
We are well on our way to 3D stacking, and something tells me the package in the new XBox will be 3D stacked, we didn't see it but its right under our noses, AMD have been building the technology bit by bit and putting it in our hands, I think the new XBox is going to be the testing ground for Ryzen, and more besides, in a GPU.
The IP patent.
http://www.freepatentsonline.com/20190196742.pdf
https://www.tomshardware.com/news/amd-3d-memory-stacking-dram,38838.html
One of the problems with 3D Stacking is interconnect bandwidth when passing data outside of the source silicon.
For example AMD's Zen and Zen+ CPU architecture is a half step to separating dies, they are monolithic in that they contain the core and uncore in a single package and split into two zones with a fabric link in the middle joining not just the two halves but an infinite loop of external monolithic dies, "Infinity Fabric"
Zen 2 is a full separation of the core and uncore.
The outer chiplets, which are 7nm, contain the cores and Caches. The central chip, which is 14nm, contains the PCIe lanes, the Memory Controllers, the IO.... and critically the Interconnect Controller IP.
This is the missing technology for true 3D Stacking, by true i'm talking about connecting stacked separate components directly to where it is needed through the component as if it was a 'vertical' piece of silicon. Like HBM.
Not just stacking components and passing data around the outside, Intel.
So you can Stack HBM on top of a GPU which is stacked on top of Core Chiplets which are stacked ontop of an IO die.
Or HBM stacked on top of GPU's, System Ram Stacked on an IO die tapping directly into the controllers.
This saves space, makes the chips overall cheaper to manufacture, increases power efficiency and performance.
We are well on our way to 3D stacking, and something tells me the package in the new XBox will be 3D stacked, we didn't see it but its right under our noses, AMD have been building the technology bit by bit and putting it in our hands, I think the new XBox is going to be the testing ground for Ryzen, and more besides, in a GPU.
The IP patent.
http://www.freepatentsonline.com/20190196742.pdf
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