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AMD Epyc has problems when you max out PCIe lanes

Soldato
Joined
1 Apr 2014
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Linus Tech Tips has an interesting video about the problems they had when they maxxed out the PCIe lanes on their Epyc server with umpteen NVME drives


TLDR There are major performance issues; it's all too fast and the bandwidth is overloaded. I'm wondering if Intel solutions have the same problems?
 
Why you try to spin it as "EPYC problem"?

Because that's what it appears to be.

And from the above post clearly you didn't understood the whole video

Are you sure? One of the highlighted problems was interrupts and processes having been switched away and the solution was to switch interrupts off and move to polling. Managing umpteen processes via polling is difficult and, as LTT found, CPU-intensive. So by reducing the number of cores you obviate that. Each process / core has more to do, of course, but it's just shifting stuff between the NIC, RAM, and the SSDs. You could do it as three processes: one moving data between the NIC and RAM, one process moving data between RAM and SSD, and one master process. That's a lot simpler with much less overhead.
 
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