AMD gpu memory controllers have for several generations been gddr5/ddr3 compatible, they are very very similar memory and have a lot in common with each other hence the cross compatibility, hence the PS4 having gddr5 and the X1 being ddr3. Strictly speaking the memory controller is still very different and they could have added compatibility for whatever the client wanted.
Either way there are quite a few rumours that seem to be pushing the idea that Kaveri will actually support gddr5, its a way to significantly increase bandwidth though latency is hurt. Thing is I'm fairly sure both because AMD helped come up with(and since alter) GDDR5, there isn't any particular reason they couldn't make some new spec gddr5 with lower total speed but lower latency(IE you can get ddr3 with cas/ras/the rest 9,9,9 and 12,12,12.
They've made high latency but very high speed gddr5, probably no reason they can't tighten the timings significantly with a small speed drop and maybe bring it to a point where its worthwhile.
Maybe they just went and did a GDDR5, but more quietly, and came up with ddr5 with Samsung on the sly to bypass DDR4 which seems, meh and to be taking donkeys years.
AMD has already gone with a Jaguar architecture with unified gddr5 access, and KAveri is said to be fully HSA compatible. With the supposed architecture changes, flooding it with bandwidth and taking the hit on access latency will hurt it badly with mispredictions I would assume, but would keep a massively higher decoder flooded with instructions.
WE'll see, AMD is certainly doing some very interesting things with Steamroller and Jaguar.
EDIT:- didn't read the whole thing, I see the article says gddr5 specifically, not ddr5. If they are talking about putting a couple chips on die for not quite gpu cache, but that could be effectively used as such, it would certainly be interesting, particularly if its all unified meaning the GPU can use the higher speed memory when it needs to, but the cpu can use it when it needs to.
Thing is AMD/Glofo/industry in general is VERY close to using transposer's for putting dies together on package, using copper traces mm's away with the ability to cram craploads of traces in a tiny area for huge bandwidth vs off die to main memory traces cm's in length that use a lot more power and are much much slower. If they stuck a few chips on a transposer and filled the main slots up with lower bandwidth/lower latency ram it would certainly be interesting but I haven't heard an awful lot that suggests transposers are ready yet, though towards the end of this year, and at GloFo, who knows.
This gen is very interesting for AMD, but when everyone gets ridiculous bandwidth on die memory via transposers then later on stacking, they will make current chips look awful in comparison.