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AMD Triple Core
- Thread starter datawrite
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Would i see a big difference between it and a 3.1 x2 AM2 in normal day to day PC work and booting etc etc?
Truth is, unless everyone here is into competition clocking, which I suspect they're not, these kind of discussions are academic. We could all happily run a mid-tier cpu from either AMD or Intel with a decent graphics card, and notice not one bit of difference in the everyday use of our machines.
Associate
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- 15 Sep 2005
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May also need to factor in how long you expect to stay until you next upgrade ... doubtless MS etc will find ways to ensure "normal day to day PC work" requires increasingly large amounts of CPU!
That said, the contrary argument is you could use saving money on the 7750X2 today as a justification for upgrading CPU later when X4's get cheaper! I can't decide which side of this fence I'm on ... though I'm leaning towards the view that the extar £60-70 for the X3 will give, via extra core and extar clocking ability, more than enouhg CPU for anything I need for couple of years at least and, whatever CPU roadmaps say my past experience has always been that by the time I think about upgrading CPU that its not a chip swap (even if this still the same socket it needs different voltages etc)
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Whats the x3 like for overclocking? people having good results?
between 3.6 & 4GHz
Associate
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i've heard that it's possible to enable more cache in X3 using Advanced Clock Calibration method (the same which is used for enabling 4-th core in X3 - see this link: http://forum.giga-byte.co.uk/index.php/topic,180.0.html ). Can anyone confirm it ?
Associate
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Think its the possibility to enable 6MB of L3 cache in the 8xxX4 AM3 PhII's ... 720X3 already has all its cache enabled.
One interesting point in the article I read about this was that the disabling of cores and L3 cache may not necessarily be due to malfunctioning silicon but be due to at present the design with all cache and all cores running consuming more power than spec-ed ... previously AMD upped there power specs which, I think, led to the exploding 780 MB situation where MBs had been designed for less power than was being used by some of the cores.
If this is true then it lends credence to the theory that the disabling of cache/core is done by some internal config registers and the ACC process (which in theory is, I think, not meant to be needed/used on PhII's) causing these to be reset to values that removed the disable flags.
