Asus motherboard question

[Drifter104]

Reading the manual for the ASUS ROG STRIX X670E-E am I right in thinking that if I want to run 3 m2 drives without dropping down to x8 on the PCIe 5.0 I would need to run them in M2_1, M2_2 & M2_4?
I'm a bit confused as the manual states if you use M2_3 the PCIe5_1 drops down to x8 and the _2 drops to x4, but there is also a table that implies if a PCIe card is used in slot PCIe_2 then PCIe_1 is dropped down to x8. Would that not also apply if something is in M2_2 slot?

 

[Tetras]

My understanding is:

M.2 slot 4 comes off the chipset and is always PCI-E 4.0.

The CPU has 24 PCI-E 5.0 lanes.

M.2 slot 1 and 2 use the spare 8 lanes (four each).

The primary PCI-E slot uses the other 16 lanes.

M.2 slot 3 shares bandwidth with the PCI-E slots (1 & 2), and since the CPU can only run 16 lanes OR 8 lanes (primary) and in this case: 4 lanes (secondary), the primary PCI-E will always drop to 8 lanes when M.2 slot 3 is used.

In summary:

You can only run 2 PCI-E 5.0 drives (slot 1 and 2) and 1 PCI-E 4.0 drive (slot 4), if you don't want to lose PCI-E lanes on the primary slot.

If you put a card in PCI-E slot 2 then the same rule applies as populating M.2 slot 3, since the CPU still has to switch to 8 lanes (primary) and in this case: 4 lanes (secondary).

 

[Drifter104]

My understanding is:

M.2 slot 4 comes off the chipset and is always PCI-E 4.0.

The CPU has 24 PCI-E 5.0 lanes.

M.2 slot 1 and 2 use the spare 8 lanes (four each).

The primary PCI-E slot uses the other 16 lanes.

M.2 slot 3 shares bandwidth with the PCI-E slots (1 & 2), and since the CPU can only run 16 lanes OR 8 lanes (primary) and in this case: 4 lanes (secondary), the primary PCI-E will always drop to 8 lanes when M.2 slot 3 is used.

In summary:

You can only run 2 PCI-E 5.0 drives (slot 1 and 2) and 1 PCI-E 4.0 drive (slot 4), if you don't want to lose PCI-E lanes on the primary slot.

If you put a card in PCI-E slot 2 then the same rule applies as populating M.2 slot 3, since the CPU still has to switch to 8 lanes (primary) and in this case: 4 lanes (secondary).

That makes more sense than what I had come up with.

Thank you

 

[Vigorito]

`does anyone know where in bios is off switch for skipping ddr5 training check in every boot cycle

 

[^JP^]

`does anyone know where in bios is off switch for skipping ddr5 training check in every boot cycle

From what I’ve been reading in preparation for my build.

“Memory Context Restore” is something to look at.

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