Borked Ballistix?

Greyhound · 13 Mar 2006 at 19:43

I think my 2 X 512Mb Ballistix PC4000 is broken.

I'm running memtest with the following settings:

DDR400 2-3-3-8

At 1T I get loads of errors in memtest at around 400mb and 700mb in test 5, at 2T I get errors around 750Mb.

Is this enough to warrant an RMA?

Should I try different RAM settings?

theredguy · 13 Mar 2006 at 21:48

Try putting them at the default settings of 2.5,4,4,8 and make sure they are getting 2.8 volts and try again mate.

trojan698 · 14 Mar 2006 at 00:37

I believe its 3-4-4-8 @ ddr500, should be able to handle those timings no probs but then I'm a sceptic, my 2gb kit just got rma'd again..

theredguy · 14 Mar 2006 at 06:48

Ah he has 2 x 512Mb not 2 x 1Gb modules though which are the same as mine from this post:

http://forums.overclockers.co.uk/showthread.php?t=17547724

they have a lower default CAS of 2.5 rather than 3 for the 1Gb sticks mate.

Greyhound · 14 Mar 2006 at 10:14

theredguy said:
Ah he has 2 x 512Mb not 2 x 1Gb modules though which are the same as mine from this post:

http://forums.overclockers.co.uk/showthread.php?t=17547724

they have a lower default CAS of 2.5 rather than 3 for the 1Gb sticks mate.

Glad you got your sticks sorted mate - would you mind posting up all of your RAM settings for me as well please?

Thanks!

theredguy · 14 Mar 2006 at 12:57

No problem mate this is how mine are set now in my DFI Lanparty UT nF4 Ultra-D. 12 hours constant loop on memtest with no faults.

DRAM Frequency Set (Mhz) By DRAM SPD Value
Command Per Clock (CPC) Auto
CAS Latency Control (Tcl) 2.5
RAS# to CAS# delay (Trcd) 04 Bus Clocks
Min RAS# active time (Tras) 08 Bus Clocks
Row precharge time (Trp) 04 Bus Clocks
Row cycle time (Trc) 12 Bus Clocks
Row refresh cyc time (Trfc) 24 Bus Clocks
Row to Row delay (Trrd) 03 Bus Clocks
Write recovery time (Twr) 03 Bus Clocks
Write to Read delay (Twtr) 02 Bus Clocks
Read to Write delay (Trwt) 03 Bus Clocks
Refresh period (Tref) 3120 Cycles
DRAM Bank Interleave Enabled

DQS Skew Control Auto
DQS Skew Value 0
DRAM Drive Strength Auto
DRAM Data Drive Strength Auto
Max Async Latency Auto
DRAM Responce Time Normal
Read Preamble Time Auto
IdleCycle Limit 256 Cycles
Dynamic Counter Disable
R/W Queue Bypass 16 x
Bypass Max 04 x
32 Byte Granularity Disable (4 bursts)

DRAM Voltage Control 2.80 V

Hope this helps mate.

Greyhound · 14 Mar 2006 at 13:01

theredguy said:
No problem mate this is how mine are set now in my DFI Lanparty UT nF4 Ultra-D. 12 hours constant loop on memtest with no faults.

DRAM Frequency Set (Mhz) By DRAM SPD Value
Command Per Clock (CPC) Auto
CAS Latency Control (Tcl) 2.5
RAS# to CAS# delay (Trcd) 04 Bus Clocks
Min RAS# active time (Tras) 08 Bus Clocks
Row precharge time (Trp) 04 Bus Clocks
Row cycle time (Trc) 12 Bus Clocks
Row refresh cyc time (Trfc) 24 Bus Clocks
Row to Row delay (Trrd) 03 Bus Clocks
Write recovery time (Twr) 03 Bus Clocks
Write to Read delay (Twtr) 02 Bus Clocks
Read to Write delay (Trwt) 03 Bus Clocks
Refresh period (Tref) 3120 Cycles
DRAM Bank Interleave Enabled

DQS Skew Control Auto
DQS Skew Value 0
DRAM Drive Strength Auto
DRAM Data Drive Strength Auto
Max Async Latency Auto
DRAM Responce Time Normal
Read Preamble Time Auto
IdleCycle Limit 256 Cycles
Dynamic Counter Disable
R/W Queue Bypass 16 x
Bypass Max 04 x
32 Byte Granularity Disable (4 bursts)

DRAM Voltage Control 2.80 V

Hope this helps mate.

Thanks for that - I'm using the NF3 ultra D so some of my bios settings may be different. Just to make doubly sure - is this your setup running at DDR400?

Thanks again!

theredguy · 14 Mar 2006 at 14:14

Yes it is mate, the board isn't in a machine yet it's on my test bench to make sure everything works first and has always run at DDR400 speeds.