Capacitor-less IGZO-DRAM Ahoy!

[jigger]

This would be the largest technological leap DRAM has ever seen and solve its biggest issue.

Disrupting the DRAM roadmap | imec

This technology review explains hpw 2T0C IGZO-based DRAM opens doors to high-density 3D DRAM and embedded DRAM.

www.imec-int.com

The capacitor has long been the problem child of the DRAM circuit, failing to scale with transistor shrinks and requiring lots engineering and material science to solve.

 

[hlennie]

wonder how long this will take to come to market

 

[Rroff]

I remember Rambus was trying to develop something similar - capacitorless twin transistor - but never got the technology working, or not enough interest. Not sure if this is their work but similar time https://www.semanticscholar.org/pap...Noda/24a78d1044ee736dadf27b127d0d350ec083ab56

 

[FredFlint]

High density dram modules cost a lot(have a lot of chips) and use a lot of power. some servers are liquid cooling the ram to deal with this. The quicker a new way is fired up the better as current dram does not scale well beyond ~12nm and uses a lot of power to keep it refreshed. I would think the big hyper-scalers and AI data centres would be pushing hard for better ram.

 

[Mr Evil]

A couple of things:

* Calling it "capacitor-less" is misleading. It stores charge in the gate of a transistor. The gate is physically two conductors separated by an insulator, which is a structure that is usually know as... a capacitor.
* The endurance looks too low to replace normal DRAM. They say it's ">10^11 read and write cycles". Let's say the CPU reads a cell, then reads it again after receiving the data (which takes something like 10ns for DDR5) and keeps doing that in a loop. It would take only 1e11 * 10e-9 = 1000 seconds to wear it out.