Yohan, Core Solo/Core Duo, are 32bit processors, with a 3 issue core (can run up to 3 instructions in parallel, and 64bit bit wide SSE (so has to make 2 64bit micro-ops for every 128bit SSE instruction), available in single, and dual core versions.
Conroe is a 64bit processor (EM64T), with a 4 issue core, +macro-op fusion, which means it can perform upto 4 instructions in parallel, but even 5 if one of them is compatible with the macro-op fusion. Conroe has full 128bit datapaths to the SSE units, so it can send single 128bit micro-ops instead of 2x64bit ones. Also available in single and dual core versions, but the single cores appear to be limited to lower clock speeds and slower fsb.
Conroe has a totally new design of branch prediction, which is supposed to be very good, and in virtually all benchmarks its looking excellent, with the exception of the sciencemark benchmarks lifted from a blog.
IMHO, once Intel release a new compiler, with options to optimize for 'Conroe' instead of P4, and someone bothers to recompile sciencemark, we'll see Conroes performance ontop there. Or it could be that sciencemark was compiled to be optimized for AMD64 anyway.
While it could be said that if intel used an onchip memory controller Conroe would be faster, its FSB is 1066, which gives a potential 8.3gb/s bandwidth, the extreme edition will have a 1333 fsb, with 10.6gb/s bandwidth, that is comparible to AM2's first edition DDR2 controller.
Even at 1066, thats enough for dual channel 533mhz DDR2 (PC4200), and with overclocking, it will have enough bandwidth for faster ram. The extreme will have enough bandwidth for DDR2 PC5300 as standard.
With its shared cache (both cores access the same 4mbx1 cache), it will reduce the performance loss intel chips normally suffer when the cores try to communicate with each other. For single chip desktops and workstations it shouldn't be a major limiting factor.
Rather than sounding like a fanboy
, AMD's hypertransport is an excellent system, and in multiprocessor machines (2 or more dual core chips), AMD should have an advantage there.
Im sure AMD will be working on something, but intel is finally going to be back in the game. As for Hypertransport, and onchip memory controllers, well intel will be replacing the standard FSB sooner or later with a system called CSI. So it seems that rather than trying to release the 'perfect' chip in one go, its going to give us a core processor now, and update the 'system/sockets' later with they are happy with the performance of CSI.