Core2Duo?

[jimbonkers]

why do, in the new conroe range, all the lower CPUs have HT and the extreme edition does not?

 

[NathanE]

Unless it has slipped past me, none of the Core 2 chips launching next month have hyperthreading.

 

[jimbonkers]

I read on a website offering preorders that it does?

 

[split]

The below is from Intel.


It's a partial truth, and partly a matter of opinion. Mobile multiple core models such as Core/duo, Merom/Conroe/Woodcrest do quite well without HyperThreading capability. Itanium/Montecito introduces a replacement for HT, called SOEMT.
The form which "many-core" will take is still a matter of research. There is a hope that work which has already been done to adapt applications to HT will show to greater advantage on multiple cores.

 

[NathanE]

I think they will bring HT back once they've moved the Core architecture to CSI (HyperTransport clone).

 

[pinkaardvark]

I thought HT came about because the P4 architecture had such long pipelines and massive latency hence HT does it's work in the gaps. Isn't the conroe just an evolution of the old p3 and hence lower latency and no place or need for HT.

 

[GAMEfreak]

think about it though. no matter how much you try to lower the latency there always WILL be a latency...

 

[NathanE]

I thought HT came about because the P4 architecture had such long pipelines and massive latency hence HT does it's work in the gaps. Isn't the conroe just an evolution of the old p3 and hence lower latency and no place or need for HT.

There a many forms of hyperthreading. Some of which work better on long pipeline designs such as NetBurst. But there are others which work just as well on short pipeline designs.

The next big leap for HT is with multi-core. By combining the execution units of all cores in the Core architecture processor, you'll have potentially much more free pipeline space to play with than there ever was in a single NetBurst pipeline. This is what Intel is keeping hush-hush about. It's also what some silly AMD spokesman coined as "the inverse of Hyperthreading" for the K10.

Also don't forget the amount of micro-ops fusion (this is where two or three uops are paired up to form one single uop, hence saving pipeline space) occuring in a Core (even Yonah) chip improves the pipeline efficiency - which potentially means more room for a HT to operate.

See here: http://www.cs.clemson.edu/~mark/multithreading.html