DDR5 JEDEC Published (Final Launch Specs)

Grim5 · 14 Jul 2020 at 21:49

tl:dr DDR5 will launch at 4800mhz and 1.2v

https://videocardz.com/press-release/jedec-publishes-new-jesd79-5-high-performance-ddr5-standard

ARLINGTON, Va., USA – JULY 14, 2020 – JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of the widely-anticipated JESD79-5 DDR5 SDRAM standard. The standard addresses demand requirements being driven by intensive cloud and enterprise data center applications, providing developers with twice the performance and much improved power efficiency. JESD79-5 DDR5 is now available for download from the JEDEC website.

DDR5 was designed to meet increasing needs for efficient performance in a wide range of applications including client systems and high-performance servers. DDR5 incorporates memory technology that leverages and extends industry know-how and experience developing previous DDR memories. The standard is architected to enable scaling memory performance without degrading channel efficiency at higher speeds, which has been achieved by doubling the burst-length to BL16 and bank-count to 32 from 16. This revolutionary architecture provides better channel efficiency and higher application level performance that will enable the continued evolution of next-generation computing systems. In addition, the DDR5 DIMM has two 40-bit fully independent sub-channels on the same module for efficiency and improved reliability.

New features, such as DFE (Decision Feedback Equalization), enable IO speed scalability for higher bandwidth and improved performance. DDR5 supports double the bandwidth as compared to its predecessor, DDR4, and will be launched at 4.8 Gbps (50% higher than DDR4’s end of life speed of 3.2 Gbps).

Additional features include:

Fine grain refresh feature: as compared to DDR4 all bank refresh improves 16 Gbps device latency. Same bank selfrefresh offers better performance by enabling some banks to refresh while others are in use.

On-die ECC and other scaling features enable manufacturing on advanced process nodes.
Improved power efficiency enabled by Vdd going from 1.2V to 1.1V as compared to DDR4.

Use of the MIPIÒ Alliance I3C Basic specification for system management bus.

At the module level, voltage regulator on DIMM design enables pay as you go scalability, better voltage tolerance for improved DRAM yields and the potential to further reduce power consumption.

“With several new performance, reliability and power saving modes implemented in its design, DDR5 is ready to support and enable next-generation technologies,” said Desi Rhoden, Chairman JC-42 Memory Committee and Executive VP Montage Technology. “The tremendous dedication and effort on the part of more than 150 JEDEC member companies worldwide has resulted in a standard that addresses all aspects of the industry, including system requirements, manufacturing processes, circuit design, and simulation tools and test, greatly enhancing developers’ abilities to innovate and advance a wide range of technological applications.”

Jamin280672 · 16 Jul 2020 at 12:40

Grim5 said:
tl:dr DDR5 will launch at 4800mhz and 1.2v

https://videocardz.com/press-release/jedec-publishes-new-jesd79-5-high-performance-ddr5-standard

What I found very interesting reading all the news, is because of the way it now communicates and pin layout etc, it will be able to run dual channel with only 1 stick of RAM, meaning we may see quad channel as standard.

4K8KW10 · 6 Aug 2021 at 05:30

ADATA Unveils XPG DDR5-12600 Overclocking Ready & DDR5-8400 Memory Kits With Up To 64 GB Capacities, Coming Later This Year
ADATA XPG DDR5-12600 & DDR5-8400 Memory Unveiled, Overclocking Support & Launching Later This Year (wccftech.com)

KompuKare · 6 Aug 2021 at 06:59

Lots of blurb, but not a single mention of latencies in the slide-deck or the article. Strange that.
Still, it looks like early adopters can spend big time as these are almost twice JEDEC spec so bound to be (even more) expensive.

Joxeon · 6 Aug 2021 at 08:35

KompuKare said:
Lots of blurb, but not a single mention of latencies in the slide-deck or the article. Strange that.
Still, it looks like early adopters can spend big time as these are almost twice JEDEC spec so bound to be (even more) expensive.

If it comes in at 12600/40 then it will have a latency of 6.3 vs the latency of 7.7 on a binned ddr4 3600/14 kit, even a 12600/48 has a latency of 7.6 so should easily be better than DDR4 although I can imagine it's not going to be cheap.

4K8KW10 · 6 Aug 2021 at 14:28

It will be years before DDR5 becomes even close to what we call "mainstream" memory.
If AMD releases its first DDR5 platform in Q4 2022, then, it's two years from now when DDR5 would begin gaining any traction in the market.

robj20 · 6 Aug 2021 at 15:15

Or should be in time for my next upgrade in a few years.
Like the idea of the dual channel per stick though.

EsaT · 7 Aug 2021 at 20:41

Jamin280672 said:
What I found very interesting reading all the news, is because of the way it now communicates and pin layout etc, it will be able to run dual channel with only 1 stick of RAM, meaning we may see quad channel as standard.

No actual extra pins for more channels.
They just split 64 bit bus width into two 32 bit pieces for more granularity of memory accessing.

Joxeon said:
If it comes in at 12600/40 then it will have a latency of 6.3 vs the latency of 7.7 on a binned ddr4 3600/14 kit, even a 12600/48 has a latency of 7.6 so should easily be better than DDR4 although I can imagine it's not going to be cheap.

You forgot front 1 from ahead of those DDR5 latency numbers.
Even slowest clock DDR5 modules released don't have that low timings and when clock speed is cranked up, timings are relaxed.

4K8KW10 · 7 Aug 2021 at 21:37

Jamin280672 said:
What I found very interesting reading all the news, is because of the way it now communicates and pin layout etc, it will be able to run dual channel with only 1 stick of RAM, meaning we may see quad channel as standard.

robj20 said:
Or should be in time for my next upgrade in a few years.
Like the idea of the dual channel per stick though.

EsaT said:
No actual extra pins for more channels.
They just split 64 bit bus width into two 32 bit pieces for more granularity of memory accessing.

I think it is a fake "dual" channel per memory module. Since the width of every channel is actually only half of what DDR4 and previous versions have to offer.

Made so to justify the notebooks vendors who always put a single memory module.

Joxeon · 8 Aug 2021 at 00:31

EsaT said:
No actual extra pins for more channels.
They just split 64 bit bus width into two 32 bit pieces for more granularity of memory accessing.

You forgot front 1 from ahead of those DDR5 latency numbers.
Even slowest clock DDR5 modules released don't have that low timings and when clock speed is cranked up, timings are relaxed.

Depends how much they will tighten when running 1.6v through them, considering Adata's saying they can get 8400mhz @1.1v then 12400 with tighter timings should be feasible @1.6v

KompuKare · 8 Aug 2021 at 07:37

Joxeon said:
Depends how much they will tighten when running 1.6v through them, considering Adata's saying they can get 8400mhz @1.1v then 12400 with tighter timings should be feasible @1.6v

The CPUs aren't even out yet, and people are already thinking on how to fry their memory controllers!
DDR5 should be on new smaller nodes not able to tolerate the old higher voltage anyhow.
The spec only moves 0.1V down to 1.1V from DDR4's 1.2V but 1.6V surely is risky for current CPU's IMC?
Also, doesn't DDR5 gives manufacturers the option to integrate voltage regulators on the DIMM and just take 1.2V and convert it as needed, so pumping more voltage through the memory chips would require being able to program those integrated regulators.

EsaT · 8 Aug 2021 at 09:23

Joxeon said:
Depends how much they will tighten when running 1.6v through them, considering Adata's saying they can get 8400mhz @1.1v then 12400 with tighter timings should be feasible @1.6v

1.6V would be over the top even for Samsung B-die DDR4 made on old 20nm node tolerating voltage better and also scaling with it.
Most DDR4 chips made on smaller nodes don't tolerate volts even that well and also usually lack B-die's scaling of timings.

And now you claim DDR5 designed for even lower voltage goes that high...
You sure are determined to not admit that DDR5 has downsides in its early years, like every preceding memory type.

Joxeon · 8 Aug 2021 at 10:38

EsaT said:
1.6V would be over the top even for Samsung B-die DDR4 made on old 20nm node tolerating voltage better and also scaling with it.
Most DDR4 chips made on smaller nodes don't tolerate volts even that well and also usually lack B-die's scaling of timings.

And now you claim DDR5 designed for even lower voltage goes that high...
You sure are determined to not admit that DDR5 has downsides in its early years, like every preceding memory type.

It's not my claim but rather what the manufacturers are saying.

EsaT · 8 Aug 2021 at 10:44

Joxeon said:
It's not my claim but rather what the manufacturers are saying.

Well, they're certainly lying about energy efficiency.
Power draw rises to square of voltage increase.
And that's assuming no decrease of resistance with voltage increase, which isn't very semiconductor like.

KompuKare · 23 Aug 2021 at 11:24

Obviously:
"If you have to ask, it's out of your range"
but Samsung had a presentation about 515GB DDR5 DIMMs at Hotchips:
https://www.anandtech.com/show/16900/samsung-teases-512-gb-ddr5-7200-modules
It all screams very expensive:

- Die stacking of 8 dies with TSV (apparently some DDR4 already does 4 stacks):

This is partnered by new cooling technologies between dies to assist with thermal performance.

- Onboard voltage controller. Looks like possible not all DIMMs will require this but this monster does:

Fully equipping a Genoa EPYC with 12 channels of 512GB would be crazy expensive, but 6TB of RAM!