The problem I have is related to the "quad pumping" of C2D chips. They can apparently make 4x (FSB speed) reads/sec from the FSB.
DDR memory on the other hand can only be accessed 2x (FSB speed) times per second.
There is talk of the best overclock for an E5200 being on a 1:1 divider and setting FSB speed to 400. However doing this would give you a chip capable of 1600 FSB reads/sec paired with memory only capable of 800 FSB reads/sec.
I don't understand how this can give any bandwidth improvement over the standard 1:2 ratio, where the ram is run at twice the FSB as the chip? Don't you need the RAM to be running twice as fast to compensate for having 1/2 as many reads/cycle?
Thus for a proper E5200 oc, wouldn't you need DDR 1600?
Why am I reading that I should find a mobo with a 1:1 divider and run some DDR2 800 RAM?
Don't get it :/
DDR memory on the other hand can only be accessed 2x (FSB speed) times per second.
There is talk of the best overclock for an E5200 being on a 1:1 divider and setting FSB speed to 400. However doing this would give you a chip capable of 1600 FSB reads/sec paired with memory only capable of 800 FSB reads/sec.
I don't understand how this can give any bandwidth improvement over the standard 1:2 ratio, where the ram is run at twice the FSB as the chip? Don't you need the RAM to be running twice as fast to compensate for having 1/2 as many reads/cycle?
Thus for a proper E5200 oc, wouldn't you need DDR 1600?
Why am I reading that I should find a mobo with a 1:1 divider and run some DDR2 800 RAM?
Don't get it :/


