3-3-3-8 = CAS Latency Control(tCL), RAS# to CAS# Delay(tRCD), Row Precharge Timing(tRP), Min RAS# Active Timing(tRAS)
CAS Latency Control(tCL)
“CAS is Column Address Strobe or Column Address Select. CAS controls the amount of time (in cycles (2, 2.5,& 3) between receiving a command and acting on that command. Since CAS primarily controls the location of HEX addresses, or memory columns, within the memory matrix, this is the most important timing to set as low as your system will stably accept it. There are both rows and columns inside a memory matrix. When the request is first electronically set on the memory pins, the first triggered response is tRAS (Active to Precharge Delay). Data requested electronically is precharge, and the memory actually going to initiate RAS is activation. Once tRAS is active, RAS, or Row Address Strobe begins to find one half of the address for the required data. Once the row is located, tRCD is initiated, cycles out, and then the exact HEX location of the data required is accessed via CAS. The time between CAS start and CAS end is the CAS latency. Since CAS is the last stage in actually finding the proper data, it's the most important step of memory timing.”
RAS# to CAS# Delay(tRCD)
”This BIOS feature allows you to set the delay between the RAS and CAS signals. The appropriate delay for your memory module is reflected in its rated timings. In JEDEC specifications, it is the second number in the three or four number sequence. Because this delay occurs whenever the row is refreshed or a new row is activated, reducing the delay improves performance. Therefore, it is recommended that you reduce the delay to 3 or 2 for better memory performance. Please note that if you use a value that is too low for your memory module, this can cause the system to be unstable. If your system becomes unstable after you reduce the RAS-to-CAS delay, you should increase the delay or reset it to the rated delay. Interestingly, increasing the RAS-to-CAS delay may allow the memory module to run at a higher clock speed. So, if you hit a snag while overclocking your SDRAM modules, you can try increasing the RAS-to-CAS delay.”
Row Precharge Timing(tRP)
”This BIOS feature specifies the minimum amount of time between successive ACTIVATE commands to the same DDR device. The shorter the delay, the faster the next bank can be activated for read or write operations. However, because row activation requires a lot of current, using a short delay may cause excessive current surges. For desktop PCs, a delay of 2 cycles is recommended as current surges aren't really important. The performance benefit of using the shorter 2 cycles delay is of far greater interest. The shorter delay means every back-to-back bank activation will take one clock cycle less to perform. This improves the DDR device's read and write performance. Switch to 3 cycles only when there are stability problems with the 2 cycles setting.”
Min RAS# Active Timing(tRAS)
”This BIOS feature controls the memory bank's minimum row active time (tRAS). This constitutes the time when a row is activated until the time the same row can be deactivated. If the tRAS period is too long, it can reduce performance by unnecessarily delaying the deactivation of active rows. Reducing the tRAS period allows the active row to be deactivated earlier. However, if the tRAS period is too short, there may not be enough time to complete a burst transfer. This reduces performance and data may be lost or corrupted. For optimal performance, use the lowest value you can. Usually, this should be CAS latency + tRCD + 2 clock cycles. For example, if you set the CAS latency to 2 clock cycles and the tRCD to 3 clock cycles, the optimum tRAS value would be 7 clock cycles. But if you start getting memory errors or system crashes, increase the tRAS value one clock cycle at a time until your system becomes stable.”
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