OCZ memory frequency

[Beerbaron]

I have just brought some OCZ 2GB PC2-6400 Dual Channel Titanium EPP-Ready Edition memory for an Asus P5B Deluxe Motherboard.

Ive just look at cpuz and the frequency is 400 mhz, surely this should be 800 mhz?

 

[Yellowbeard]

CPU-Z is correct as 400mhz is the actual frequency of DDR800/PC6400 memory. However it transfers data 2 times per cycle so the effective data rate is 800, aka Dual Data Rate 800.

 

[Beerbaron]

brilliant thanks mate

 

[Reality|Bites]

Although DDR2 transfers data 4 times per cycle, twice on the rising and twice on the falling end of the cycle.

 

[Yellowbeard]

Although DDR2 transfers data 4 times per cycle, twice on the rising and twice on the falling end of the cycle.

Actually no, it doesn't. It is 2 times per cycle.

 

[Reality|Bites]

Yes it does

http://www.xbitlabs.com/articles/memory/display/ddr2-ddr_2.html

 

[Yellowbeard]

Not only is that article from 2004, it is wrong. IMO, based on past articles, don't trust anything that author presents. Do some research, you'll find it. Both DDR and DDR2 transfer data on the rising edge and falling edge of each clock cycle. It's 2 times per cycle and there is no multiplexing or whatever rubbish that guy is spouting.

http://www.corsairmemory.com/corsair/products/tech/memory_basics/153707/index.html

http://en.wikipedia.org/wiki/Double_data_rate


http://searchmobilecomputing.techtarget.com/sDefinition/0,,sid40_gci523855,00.html



I can only guess he is hallucinating about bank interleaving or adding the 2 individual channels of a dual channel system together.


EDIT: Read the entire article, esp the charts on page 5. Do you really think DDR2 memory is transferring 2x as much data as DDR?

 

[Reality|Bites]

again, Yes it does

http://en.wikipedia.org/wiki/DDR2_SDRAM

 

[Yellowbeard]

I think have confused the semantics of the info here.

The key difference between DDR and DDR2 is that in DDR2 the bus is clocked at twice the speed of the memory cells, allowing transfers from two different cells to occur in the same memory cell cycle. Thus, without speeding up the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR.

Each cell is still transferring 2 times per cycle which I did not clarify earlier. Your statement is true and I concede the point on a total of 4 transfers per cycle due to simple frequency increase. 2 cells can transfer per cycle due to the higher bus frequencies however, each cell is still only transferring than 2 times per cycle.

In a nutshell, it is simply more transfers per clock due to a higher frequency as the cells are signaled 2x as fast. I am sorry, I did not make my point clear.

 

[Reality|Bites]

So yes you do get 4 transfers per cycle with DDR2 compared to 2 transfer per cycle with DDR or not?