When overclocking CPU clock is king! Faster you over clock the speed of the processor the more voltage core (Vcore) you may have to apply to allow it to run stable! General rule of thumb more volts = more heat due to greater power consumption. Leaving Vcore on auto on some motherboards may overshoot the voltage required by a fair margin, resulting in needless increased temperature. So manual voltage is recommended here to counteract this.
To give you an insight, all data is transmitted on a BUS, synchronised by a clock speed usually megahertz (MHz) or gigahertz (GHz) and there are a number of complex controls which command how and when it is transmitted, this also goes for memory. Modern RAM DDR (Dual Data RAM) does what is says on the tin, it can transmit and receive in one clock cycle. This is why the RAM speed may show up as 800MHz, which is effectively 1600MHz as it uses the rise and fall slopes of the clock pulse.
Ram timings are explained here:
CAS: Column Address Strobe, defines the time it takes for data to be ready for burst after a read command is issued. As CAS factors in almost every read transaction, it is considered to be the most important timing in relation to memory read performance.
To calculate the actual time period denoted by the number of clock cycles set for CAS we can use the following formula:
• tCAS in Nano seconds=(CAS*2000)/Memory Frequency
This same formula can be applied to all memory timings that are set in DRAM clock cycles.
DRAM RAS TO CAS Latency: Also known as tRCD. Defines the time it takes to complete a row access after an activate command is issued to a rank of memory. This timing is of secondary importance behind CAS as memory is divided into rows and columns (each row contains 1024 column addresses). Once a row has been accessed, multiple CAS requests can be sent to the row the read or write data. While a row is “open” it is referred to as an open page. Up to eight pages can be open at any one time on a rank (a rank is one side of a memory module) of memory.
DRAM RAS# PRE Time: Also known as tRP. Defines the number of DRAM clock cycles it takes to precharge a row after a page close command is issued in preparation for the next row access to the same physical bank. As multiple pages can be open on a rank before a page close command is issued the impact of tRP towards memory performance is not as prevalent as CAS or tRCD – although the impact does increase if multiple page open and close requests are sent to the same memory IC and to a lesser extent rank (there are 8 physical ICs per rank and only one page can be open per IC at a time, making up the total of 8 open pages per rank simultaneously).
DRAM RAS Active Time: Also known as tRAS. This setting defines the number of DRAM cycles that elapse before a precharge command can be issued. The minimum clock cycles tRAS should be set to is the sum of CAS+tRCD+tRTP.
DRAM Command Mode: Also known as Command Rate. Specifies the number of DRAM clock cycles that elapse between issuing commands to the DIMMs after a chip select. The impact of Command Rate on performance can vary. For example, if most of the data requested by the CPU is in the same row, the impact of Command Rate becomes negligible.
These are the numbers you will see associated with RAM mine runs at 8-8-8-24 1T for instance at 1.5V. The Intel Xtreme Memory Profile or XMP for my RAM is 9-9-9-24 2T at 1.25V so here I have "tightened" my timings against the JEDEC standard (JDEC is the global leader in developing open standards for the microelectronics industry, with more than 3,000 volunteers representing nearly 300 member companies) this effectively increases the performance of my RAM by decreasing the wait states between clock cycles.
Reduce Timings in This Order:
Command rate – Go from 2T to 1T (or 2N to 1N, depending on what your board calls them). This is the easiest change to make and most kits will have no problem with this change.
tRP – Try reducing by one or two. This timing is relatively forgiving, but is a little more difficult than tRAS in the next step.
tRAS – Try reducing by two to five. Of the four primary timings, this one is the easiest to reduce.
tRCD – Try reducing by just one. It gets harder with this timing. You might not be able to reduce it at all.
CL – This is the trickiest and is more difficult to tighten than tRCD. Try just one here as well, but expect you won’t be able to reduce it, depending on how far you had to reduce your memory speed. If you can reduce it, this will have the biggest impact on benchmark results.
To overclock your RAM you will have to adjust the BCLK and or RAM:FSB ratio. The Front Side Bus (FSB) or BCLK is the base clock from which all frequencies are derived! This has to be done with care, as you will have to lower your CPU multi also when attempting this. Also ensure other Buses, PCIe, etc. are locked at 100MHz. This introduces then other things like PLL voltages, LLC (Load Line Calibration) levels - this ensures that at maximum current draw, (vdroop) the voltage drops, Ohms Law! because of this, the VRMs will compensate and deliver more juice to help keep the voltage level and stable. Overclocking in my experience can be very time consuming and complicated. I for now would just dial in a voltage and multi for the CPU, leave the RAM on XMP. Then check stability and temps using a stress testing program, and lower the voltage after successfully running, until it is unstable or BSOD, stop 124 error or 9c. Then you have your stable overclock! Good luck and enjoy your new setup!
