Revolutionary CPU design "VISC" to make threading transparent, solve IPC woes

[Orangey]

http://wccftech.com/amd-invest-cpu-ipc-visc-soft-machines/
http://semiaccurate.com/2014/10/23/soft-machines-breaks-cover-visc-architecture/
http://www.kitguru.net/components/c...cture-vows-2-4-times-performance-improvement/
http://techreport.com/news/27259/cpu-startup-claims-to-achieve-3x-ipc-gains-with-visc-architecture

Pick your poison, wccf has most pics.

First up it stands for Virtualized Instruction Set Computing and utilizes a new type of front bus which shuttles instructions in groups ("threads") to virtual cores which can be beefed up or down depending on workload. A virtual core can apportion resources from multiple real cores.

A startup company by the name of Soft Machines has just exited its “stealth” phase and gone public for the first time at the Linley Processor Conference. Which many startups go through to ensure that their ideas are protected and their principal goals are met before they go public.

“The VISC architecture achieves 3-4 times more instructions per cycle (IPC), resulting in 2-4 times higher performance per watt on single- and multi-threaded applications. Moreover, VISC uses a light-weight “virtual software layer” that makes VISC architecture applicable to existing as well as new software ecosystems.” The company claimed in its press release.

Here is what the ex-Intel head honcho has to say:

CPU scaling was declared dead when the power wall forced CISC- and RISC-based designs into multi-core implementations that require unrealistically complex multi-threading of sequential applications. The VISC architecture solves this problem ‘under the hood’ by running virtual hardware threads on virtual cores that far exceed the efficiency of software multi-threading.

Here's some more analysis:

The technology works by allowing multiple CPU cores to work on a single software thread. Something that was previously thought impossible. The company didn’t go into the specifics of how this is achieved but they state that it’s compatible with any ISA (Instruction Set Architecture). Meaning we could very well see this technology adopted by Samsung and AMD in ARM and x86 CPU architectures.

This is obviously important because it enables performance gains in single threaded applications when using multi-core CPUs. We no longer have to be as reliant on the software to be smart enough to fully utilize a multi-core CPU. And that’s indeed an exciting prospect to ponder upon if only briefly.

Looks interesting.

 

[Orangey]

Yup when I first saw the headlines I immediately thought of CMT (clustered multi threading) which incidentally is being dropped in favour of traditional SMT (simultaneous multi threading) in Zen.

AMD are investors btw.

I wonder what this means for HSA/hUMA? Does it slot in neatly?

 

[Orangey]

God, the Killer NIC. I'm afraid to look it up as it will quite possibly make me feel very old. I think it was around at the same time as Ageia.

 

[Orangey]

I think they still sell that feature as Virtu MVP. It is not allowed in some bench threads I've seen.

http://lucidlogix.com/products/virtu-mvp-2-0-for-windows/

 

[Orangey]

It was the Big Bang, I remember the hype, then it kind of just went away quietly. However scaling has gotten amazingly good since then, a shame that mixed vendor seems doomed to be nothing more than a pipe dream though.

 

[Orangey]

This is why spoffle is b& from Graphics Cards

 

[Orangey]

They want to do like ARM and license their designs, potentially way more money than simply being bought out. Then again if Intel does buy it and it works, their engineering force will get it to market very quick.

 

[Orangey]

They say there is only a 5% hit when translating between ARM and native instruction sets. If this holds true for other ISAs then it's HSA dream come true.

 

[Orangey]

Already commercializing:

http://www.eetimes.com/document.asp?doc_id=1327933&page_number=1

What a breath of fresh air to see something exciting actually make it to market for once...

 

[Orangey]

It takes multiple real cores/threads and spreads the load across virtual ones. So I think that fits the description.

It also has a translation layer between ISAs (eg - X86, ARM) with reportedly only a 10% hit.

 

[Orangey]

It was founded by Intel alums, I'm sure that will help.

 

[Orangey]

If Intel see them as an antagonist, that could be a problem.

After all it does seem like this would allow ARM to finally break into servers and not require customers to change their software stack. IIRC Intel has the market completely sewn up atm.