Sandy Bridge question

[Stickman]

Has there been any details yet on the RAM controller that will be in the HEDT versions of Sandy Bridge (B2) CPUs?

The wikipedia article has the lower end chips RAM speeds listed as "maximum 25.6 GB/s bandwidth, supports DDR3-1600 dual channel RAM" but I notice the high end version in the table supposedly has a peak memory bandwidth of 51.2 GB/s from 4 x DDR3-1600... which might suggest it's quad-channel to get that kinda bandwidth, but I can't seem to find anything on the net yet to confirm that. All the articles I've seen talk about dual-channel on the low-end and triple channel on the high end, but can triple channel DDR3-1600 really hit that bandwidth?

edit: ah - I think I see where the confusion is from: If this table is accurate, looks like the quad-channel ram is reserved for the server/workstation CPUs:
http://pc.watch.impress.co.jp/img/pcw/docs/360/112/1.jpg
The desktop ones (even high-end) still list 3ch DDR3.

 

[nightmare99]

The mainstream parts will appear much sooner than the high end ones and sample chips are about. I don't think there is any reliable information about the high end parts bar perhaps the pin count which support the theory that they will be quad channel DDR3.

 

[D1ngd0ng]

Think I read something in CPC/on Bit-Tech forum that said the mem controler would be quad channel but would need to go back and check again to be 100%

 

[Magic Man]

When is mainstream/desktop SandyBridge due?

 

[nightmare99]

Dec/Jan

 

[pastymuncher]

Going by this article very soon.