*** ***Intel Core i7 920 D0 Stepping (SLBEJ) 2.66Ghz (Nehalem) (Socket LGA1366) - Retail @ £201.99 inc VAT *** ***
Ultra Overclockable D0 Stepping (SLBEJ) Version to allow the highest overclocks and lowest temperatures possible. Achieve 975 performance at 920 pricing.
Nehalem is a radically new design for Intel: for the first time, the CPU is a 'native' quad-core CPU, where all four cores sit on the same piece of silicon. With its Core 2 CPUs, Intel used two dual-Core dies to create a quad-core chip, this translates into better performance. Nehalem features Level 3 cache, something first seen on earlier Xeon server chips, but Intel Core i7s will feature up to a massive 8MB (shared between all four cores). Each of Nehalem's four cores has 256KB of lower-latency Level 2 cache.
The Level 3 cache of Nehalem is described as being ‘inclusive’, meaning that it holds the data of all the Level 2 caches. This means that if a core needs to fetch data, and it doesn’t find it in the Level 3 cache, it can be confident that the most up-to-date version of that data is held in system memory and fetch straight from there. If the Level 3 cache wasn’t inclusive, the core would first have to look at the cache of the other three cores to ensure that none of them had a more recent version of the data it needs. An inclusive cache is therefore said by Intel to be more efficient than an ‘exclusive’ cache design, even if it does mean that 1MB of Nehalem’s 8MB Level 3 cache is taken up by storing a copy of the 256KB Level 2 cache inside each processing core, again this translates into a performance gain over Intels previous designs.
Intel has integrated the memory controller onto the Nehalem CPU die rather than having it be part of the Northbridge on the motherboard. It's achieved this by modularising the design of the CPU. The seperate processing cores and caches are linked to the onboard memory controller via a new bus standard called QuickPath (sometimes called QPI, short for QuickPath Interconnect). As QuickPath replaces the Frontside Bus (FSB) and Northbridge combo, it also takes over the role of allowing the CPU to connect to other system components, busses and controllers such as the PCI Express controller and DDR3 memory.
The last big news about Nehalem is that it uses Hyper-Threading. This technology works just as it did with the Pentium 4, using spare resources of a processing core to try to execute a second process thread. This means that a quad-core Nehalem processor can accept and attempt to process eight threads simultaneously, making it even more massively parallel than the current Core 2 Quad CPUs.
- Lithography Process: 45 nm
- Cores: 4
- Threads: 8
- Frequency: 2.66 GHz
- Cache: 256 KB L2/core and 8 MB shared L3
- Memory Controller: Triple channel DDR3 800/1066/1333 MHz
- Bus Interface: 1x 4.8 GT/s QuickPath
- TDP: 130W
- Socket: LGA1366
- D0 Stepping (SLBEJ) for extreme Overclocking
Only £201.99 inc VAT
ORDER NOW
Ultra Overclockable D0 Stepping (SLBEJ) Version to allow the highest overclocks and lowest temperatures possible. Achieve 975 performance at 920 pricing.
Nehalem is a radically new design for Intel: for the first time, the CPU is a 'native' quad-core CPU, where all four cores sit on the same piece of silicon. With its Core 2 CPUs, Intel used two dual-Core dies to create a quad-core chip, this translates into better performance. Nehalem features Level 3 cache, something first seen on earlier Xeon server chips, but Intel Core i7s will feature up to a massive 8MB (shared between all four cores). Each of Nehalem's four cores has 256KB of lower-latency Level 2 cache.
The Level 3 cache of Nehalem is described as being ‘inclusive’, meaning that it holds the data of all the Level 2 caches. This means that if a core needs to fetch data, and it doesn’t find it in the Level 3 cache, it can be confident that the most up-to-date version of that data is held in system memory and fetch straight from there. If the Level 3 cache wasn’t inclusive, the core would first have to look at the cache of the other three cores to ensure that none of them had a more recent version of the data it needs. An inclusive cache is therefore said by Intel to be more efficient than an ‘exclusive’ cache design, even if it does mean that 1MB of Nehalem’s 8MB Level 3 cache is taken up by storing a copy of the 256KB Level 2 cache inside each processing core, again this translates into a performance gain over Intels previous designs.
Intel has integrated the memory controller onto the Nehalem CPU die rather than having it be part of the Northbridge on the motherboard. It's achieved this by modularising the design of the CPU. The seperate processing cores and caches are linked to the onboard memory controller via a new bus standard called QuickPath (sometimes called QPI, short for QuickPath Interconnect). As QuickPath replaces the Frontside Bus (FSB) and Northbridge combo, it also takes over the role of allowing the CPU to connect to other system components, busses and controllers such as the PCI Express controller and DDR3 memory.
The last big news about Nehalem is that it uses Hyper-Threading. This technology works just as it did with the Pentium 4, using spare resources of a processing core to try to execute a second process thread. This means that a quad-core Nehalem processor can accept and attempt to process eight threads simultaneously, making it even more massively parallel than the current Core 2 Quad CPUs.
- Lithography Process: 45 nm
- Cores: 4
- Threads: 8
- Frequency: 2.66 GHz
- Cache: 256 KB L2/core and 8 MB shared L3
- Memory Controller: Triple channel DDR3 800/1066/1333 MHz
- Bus Interface: 1x 4.8 GT/s QuickPath
- TDP: 130W
- Socket: LGA1366
- D0 Stepping (SLBEJ) for extreme Overclocking
Only £201.99 inc VAT
ORDER NOW
