Associate
- Joined
- 29 Jan 2007
- Posts
- 731
If you read around the net, all sorts of little formulae pop up regarding setting tRAS and tRC. These two settings are like the dark sheep of the family, with conflicting information about what they should be.
Even memory SPD's and motherbaords seem to set them differently and their values massively increased out of proportion to so called formulae as mem speeds passed 400Mhz.
For example, we went from 3-3-3-12-16@533 (tRAS 12 tRC 16), to 4-4-4-18-23@800 and beyond. tRAS and tRC bumping up exponentially with Mhz.
Yet people still try and set them really low. The only settings I have ever changed are the first three timings tCL-tRCD-tRP and the command rate (if possible), as I just don't know what the hell I'm doing with the rest - plus they don't seem to have any percievable performance gain.
Has anyone ever found a performance gain from lowering tRAS, tRC and the other less common timings? The way they increase in a non-liner fashion with Mhz must mean they need to be set high for some reason, perhaps stability with the high cycle speeds, so why do people force them down low?
I'd love to get a memory engineer to explain it, but my own tests seem to suggest leave everything on auto and stick to changing the ones with real gains - tCL-tRCD-tRP.
Even memory SPD's and motherbaords seem to set them differently and their values massively increased out of proportion to so called formulae as mem speeds passed 400Mhz.
For example, we went from 3-3-3-12-16@533 (tRAS 12 tRC 16), to 4-4-4-18-23@800 and beyond. tRAS and tRC bumping up exponentially with Mhz.
Yet people still try and set them really low. The only settings I have ever changed are the first three timings tCL-tRCD-tRP and the command rate (if possible), as I just don't know what the hell I'm doing with the rest - plus they don't seem to have any percievable performance gain.
Has anyone ever found a performance gain from lowering tRAS, tRC and the other less common timings? The way they increase in a non-liner fashion with Mhz must mean they need to be set high for some reason, perhaps stability with the high cycle speeds, so why do people force them down low?
I'd love to get a memory engineer to explain it, but my own tests seem to suggest leave everything on auto and stick to changing the ones with real gains - tCL-tRCD-tRP.
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