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UTBB FD-SOI process tech coming to GlobalFoundries

Orangey

Orangey

Orangey

Soldato
Joined
22 Aug 2008
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http://www.st.com/web/en/press/c2720

28nm with 14nm coming too. Here is some pertinent info:

The launch of Places2Be, a 3-year, €360M advanced-technology pilot-line project to support the industrialization of Fully-Depleted Silicon-On-Insulator (FD-SOI) microelectronics technology was announced today by a group of 19 leading European companies and academic institutions.

Led by STMicroelectronics (NYSE: STM), a global semiconductor leader serving customers across the spectrum of electronics applications, Places2Be (“Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe”) aims to support the deployment of a FD-SOI pilot line at 28nm and the subsequent node, as well as a dual source that will enable volume manufacturing in Europe. Places2Be will drive the creation of a European microelectronics design ecosystem using this FD-SOI platform and explore the path towards the next step for this technology (14/10nm).

FD-SOI is a low-power, high-performance next-generation alternative to conventional (“bulk”) silicon and FinFET technologies. The first FD-SOI systems-on-chips are expected to be used in consumer electronics, high-performance computing and networking.
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FD-SOI stands for “Fully-Depleted Silicon-On-Insulator.” This technology improves the electrostatic control of the transistor channel, improving transistor performance and power efficiency. More precisely Places2Be uses Ultra-Thin Body and Buried oxide (UTBB) FD-SOI, which allows the dynamic tuning of transistor performance, from low power to high speed, during operation.
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The bolded bit is how Maxwell achieves the power consumption figures it does. Such features (faster power gating etc) are visible on an AMD roadmap slide that humbug was posting quite a lot recently. Now we know the ends to the means of how they will deliver it.

I wonder if there's any interest for a sticky or general thread about process tech, as a lot of these stories are follow-ups and tie in together.
 
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AFAIK Maxwell is on standard planar 28nm TSMC doesn't currently support fdsoi, while it uses similar techniques (far more granular control over what parts of the GPU are running at full speed for any given operation) its not advanced down to individual transistor level which would give it another significant boost again.

EDIT: To avoid confusion as the whitepaper is a bit misleading at facevalue - Maxwell has design time optimisation tuned down to the transistor level but not run time dynamic optimisation at transistor level.
 
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Yup, I should've ended the bold before "during operation". :)

Just meant that the general idea is what we've seen touted already in Maxwell.
 
Seems like TSMC are looking at adding FDSOI in the same footprint as bulk planar... another round of 28nm GPUs before we see anything smaller? :D
 
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