Fully static CMOS design. This has eradicated the use of high speed logic, which uses up a relatively large amount of power for the same effect.
These are replaced with more parallelised logic, which are larger and slower but more numerous. This still results in a net reduction in power consumption in most situations.
This increase in logic forced the engineer's hand on the touchy subject of cache, which has been the sticking point for many arguments around the community.
This means that in some situations the chip performs less than optimally (3D games being a key example) when compared to the previous chips.
Hyperthreading this time around has been implemented better than on the Netburst architecture. When an application does not benefit, it simply doesn't influence power consumption, but when it does it offers a significant extra pathway of performance and (a relatively small) increase in power consumption.
With Nehalem, Intel is
also introducing a technology that it calls "power gating." Traditionally, Intel has been able shut down an unused core by cutting its active power, but even though it's in a sleep state, that core is still dissipating plenty of power because of leakage current. Intel's power gating technique involves a new transistor design, and it lets Intel cut the leakage current, as well, so that the sleeping core's power dissipation drops to near zero.
When one or more of the cores on a Nehalem chip are powered down, the processor can divert extra power to the cores that are in use by increasing their clockspeed and voltage. This gives the active cores extra performance headroom while permitting the overall processor to remain in the same power envelope.
Not to mention the PCU and all the added Micro Op goodness that provides, you're looking at a significantly more efficient chip.
