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TSMC has postponed the installation of its 16nm production lines to the second half of 2015 instead

Boomstick777

Boomstick777

Boomstick777

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Oh joy :(

28nm 4eva..

TSMC to face tough questions on Qualcomm orders
Steve Shen, DIGITIMES, Taipei [Wednesday 14 January 2015]

Taiwan Semiconductor Manufacturing Company (TSMC) is to face a slew of tough questions to be asked by institutional investors at its upcoming investors conference to be held on January 15.

TSMC is expected to clarify the latest market speculations indicating that Qualcomm reportedly has put a halt on trial production of its next generation chips built using a 16nm FinFET process at TSMC as reported by the Chinese-language Liberty Times on January 14.
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http://www.digitimes.com/news/a20150113PD206.html
 
A significant improvement of yield rates of 14nm FinFET process at Samsung Electronics is the main reason for Qualcomm to halt its trial production at TSMC, said the paper.
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Could we just skip to 14Nm instead and thats why they are stopping 16?
 
I wonder if we'll see 10nm before 2020. It seems that they really are hitting a wall making things smaller. There have been so many problems and the costs are spiralling upwards, perhaps making it financially not viable.

There is no guarantee that we'll get any more shrinks in a timely manner.
 
I hope it's backwards compatibility* holding them back in the teens and not something that will be repeated ad nauseum at 10nm+.

*16nm uses the same metal layers as 20nm so customers could port designs easily. Although hardly anyone used 20nm so eh.
 
Taking the **** now, I've held off Maxwell waiting on a die shrink.

Not been keeping track but are they skipping 20/22nm? and going straight to 16nm?

Will we now see them not skip 20/22nm with this added delay?

And on a side note, for example a 28nm Maxwell 970 has a TDP of 145w, will shrinkin the die by almost half to 16nm = 50% tdp reduction for the same performance, or doesn't it work like that?
 
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Basically yes, if all you did was take a 970 and shrink it to 16nm finfet+, you would halve its power usage (up to 70% power saving according to tsmc, but i would take that with a pinch of salt)
 
Orangey said:
I hope it's backwards compatibility* holding them back in the teens and not something that will be repeated ad nauseum at 10nm+.

*16nm uses the same metal layers as 20nm so customers could port designs easily. Although hardly anyone used 20nm so eh.
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It's got nothing to do with backwards compatibility, 16 and 14nm finfets(from tsmc and samsung/glofo respectively) ARE 20nm processes. They are being called something less for no reason other than the electronic advantage from finfets is somewhat worth calling it a different node AND because Intel has been consistently lying(to a greater degree) about their node size for so long they'd look poor in comparison.

There is no backwards compatibility issue at all, it's 20nm with finfets, nothing more or less.

The trouble is finfets and Intel's 14nm finfets are faring no better really. There is a reason Broadwell has been MASSIVELY delayed, has had it's promised advantages scaled back from early days with promises of 20% better performance to now 4%, and that is largely BS. AFAIK their 22nm mobile chips can run at 2-2.5Ghz with as low as 0.8v or something, the similar 14nm chips are now pushing 1.05v or something for 1.6-2Ghz range. Everyone is struggling very badly getting the voltages and yields on smaller finfets.

Intel's 22nm had a 84nm metal pitch which is what GloFo was achieving on 28nm, I think TSMC were around 90nm on their 28nm.

While Intel is doing something closer to a real 14nm, it's metal pitch is still 64nm, which is the same TSMC/GloFo/Samsung are achieving on their 20nm. It's somewhat the limit with current equipment, dual patterning and current wavelength of light being used.

10nm is likely to face a lot of new problems. Intel is on I think they say 3rd gen finfets but struggling badly. Everyone else is struggling even worse on 1st gen finfets, the common thing being size. It's quite likely that FD-SOI at 20-14nm FD-SOI might be the go to higher power using process nodes.

However the "rumour" is utterly bogus, won't install equipment till Q3, nonsense. Firstly most of the equipment is the same as the 20nm process because it is 20nm. there are basically 10-15% extra machines, not for any real difference just because different machines make some of the stages of making the finfets. This equipment would need to be in place like a year before mass production, they've already stated they've been in risk production and run test chips and the like meaning the equipment(much of it) has to be there already. There are of course stages of upgrading. YOu might upgrade one of say 4 or 6 lines in a fab at a time so 80% of capacity continues producing while only 20% is offline. YOu play around with that, learn a lot then bring another line down at a time to upgrade, etc, etc. So SOME equipment may have been delayed.
 
^^ I doubt we will see true 10nm for quite a long time - what most companies have pencilled in as "10nm" is basically anything sub 19nm planar.
 
EUV will probably be really interesting for the industry, it will switch everything back to single patterning which will do everyone a world of good on costs, volume/manufacturing time(dependant on each other heavily), likely yields but... wow, when you read up on EUV it's genuinely amazing the amount of issues and hurdles it has already and others that still need to be overcome. It is insanely complex and frankly quite brilliant, I absolutely in no way claim to understand it fully at all, not even close, I only understand enough to understand just how complex it is to get working.
 
I read something a little while ago about "pellicles" and the problems with them needing to be 100% clean, but all I really took away from it is it's amazing any chips get made at all.
 
So much for Moore's law. We are settling into a ~25% performance increase per generation and it is pathetic.
 
All/most of the low hanging fruit has been picked, so they are now up against a truly massive engineering task to get any 'new' process right.
 
ICDP said:
So much for Moore's law. We are settling into a ~25% performance increase per generation and it is pathetic.
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If they can't shrink, then don't take that 25% increase each gen fore-granted.

Because both nV and AMD may end up like Intel with 5% increases each gen.

We may even look back on this time with fondness. "Remember when we got a 20% increase each gen? Those were the days..."
 
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