Canard mentions second gen' EPYC, if true, nice!

[Fishbait]

Ne le répétez à personne, mais les CPU EPYC de 2e gen d'AMD auront 64 cores, 256 Mo (!) de L3, 8x DDR4-3200 et 128 lignes de PCIe 4.

Second gen' AMD EPYC cpu will have (upto) 64 cores, 256mb of L3, 8*DDR4-3200 & 128PCIe-4 lines.

https://twitter.com/x/status/925348852147908608

 

[humbug]

What? thats insane!!!!! :O

 

[Scougar]

Can someone please explain the difference between current EPYC and this new version please?

 

[humbug]

Can someone please explain the difference between current EPYC and this new version please?

Current EPYC:

32 Core 64 threads
128MB L3 Cache?
8 Channel DDR4 @ 2666Mhz
128 PCIe 3 lanes

New EPYC:
64 Core 128 threads
256MB L3 Cache
8 Channel DDR4 @ 3200Mhz
128 PCIe 4 lanes

 

[AndreiD]

@Scougar Current Epyc is up to 32 cores, according to that rumor tweet the next gen Epycs will be up to 64 cores.

Since Epyc is an MCM of 4x 8C Ryzen dies, AMD will either scale that to 8 dies or they'll make 16C dies.
8 dies in my opinion seems unlikely, the Epyc package is already gigantic and TDP will become a pretty big concern with so many dies, not to mention the interconnect latency will muddy performance. AMD making a 16 core die and using 4 of those in an MCM design seems plausible, it could be quite possible in a similar die area as a current Ryzen if they move to a denser process (possibly GloFo's 7LPE, but I'm not sure that's going to be dense enough since it's realistically closer to a 12~10nm process).

 

[jigger]

Could be built at TSMC.

 

[Rroff]

Could be built at TSMC.

Rumour is they are using TSMC's 7nm for the high end CPUs where they can absorb the penalty for not using GF in the price. It is the only way they are making a 4x 16C package IMO.

(The agreement is per wafer costing so they can't really leverage that from lots of mid-range dies, etc. AFAIK - they need products with big margins).

 

[jigger]

Shrugs. I've no idea what AMD will do or what level of profit they need.

It could be built at global.

 

[SupraWez]

Now that would be EPYC

Dual socket board would equal 128 cores, 256 threads....

 

[humbug]

Shrugs. I've no idea what AMD will do or what level of profit they need.

It could be built at global.

The same people who posted this 'Canard' also predicted Ryzen and EPYC, correctly... they also publish a run down on EPYC costs to AMD, i forget the exact figure but the CPU was $150 assembled and shipped, in other-words it cost AMD a total of $150 to sell one EPYC CPU, so anything they sold it as above $150 was money in their pockets.

Because of the modular design they are getting excellent yields on them, something like 80 to 90%, again according to Canard.

 

[Scougar]

Current EPYC:

32 Core 64 threads
128MB L3 Cache?
8 Channel DDR4 @ 2666Mhz
128 PCIe 3 lanes

New EPYC:
64 Core 128 threads
256MB L3 Cache
8 Channel DDR4 @ 3200Mhz
128 PCIe 4 lanes

Wow!! Well that was a little unexpected!!!

As a side note.... 3200mhz ram official support... AMAZING.

Bodes well for Ryzen.

 

[jigger]

AMD have a micro code update for 4000Mhz memory. That would be bandwidth ahoy with 8 channel memory.

 

[Rroff]

Shrugs. I've no idea what AMD will do or what level of profit they need.

It could be built at global.

AMD paid a fair bit of money to get the WSA with GF amended, which they wouldn't have done just for fun, and part of the agreement is that they pay on a per wafer basis for anything produced elsewhere - with the current terms it isn't commercially viable on products that aren't big ticket/high margin.

From the looks of things to produce 16C dies usable in such a configuration wouldn't really be possible without EUV on GF 7nm while TSMC has a bit better DUV lithography allowing for smaller minimum gate pitch, etc. on their first 7nm process which might just about make it possible. (People can BS about GF - but 16nm shows just how big a margin there in in reality between TSMC and GF's lithography and maturity and the first round of 7nm without EUV will rely on that).

To quote someone else heh:

"GloFo has managed to get AMD to pay for GloFo's own incompetence -- and do so twice!"

 

[jigger]

AMD paid a fair bit of money to get the WSA with GF amended, which they wouldn't have done just for fun, and part of the agreement is that they pay on a per wafer basis for anything produced elsewhere - with the current terms it isn't commercially viable on products that aren't big ticket/high margin.

From the looks of things to produce 16C dies usable in such a configuration wouldn't really be possible without EUV on GF 7nm while TSMC has a bit better DUV lithography allowing for smaller minimum gate pitch, etc. on their first 7nm process which might just about make it possible. (People can BS about GF - but 16nm shows just how big a margin there in in reality between TSMC and GF's lithography and maturity and the first round of 7nm without EUV will rely on that).

To quote someone else heh:

"GloFo has managed to get AMD to pay for GloFo's own incompetence -- and do so twice!"

Yeah I know. I told you about AMD's deal with TSMC if you remember.

 

[CAT-THE-FIFTH]

So a single Ryzen 2 chip will be 16c/32t??

 

[humbug]

So a single Ryzen 2 chip will be 16c/32t??

 

[Rroff]

Yeah I know. I told you about AMD's deal with TSMC if you remember.

You mentioned a supposed big order had been placed in the context of GPUs - which seems to be just someone's interpretation of the WSA amendment. As I said wouldn't surprise me if they did go back to TSMC.

 

[Panos]

So a single Ryzen 2 chip will be 16c/32t??

More likely.

 

[Scougar]

So a single Ryzen 2 chip will be 16c/32t??

That would be EPYC.... (IGMC).

But I highly doubt we are going from 4C to 16C.

 

[WingZero30]

This is impressive stuff from AMD !!!

I wonder what intel would do to try to counter it ?