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AMD Zen 3 (5000 Series), rumored 17% IPC gain.

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GregI said:
Zen3 FP IPC Gain ～10%, Int IPC Gain >> 10%. ST perf (Frequency + IPC) Gain 15-20%.
Cinebench R20 Single thread over 600 points if these leaks are correct (can't see why they wouldn't be). According to the Overclockers UK database the rank 1 score for ST CB20 is 601 by a 9900k at 5.7 Ghz.
Zen 3 is basically going to be a 5.75 Ghz 9900k.
Click to expand...

I'd be amazed if they break 600 on single core.
That would be a massive uplift, if they do it'll be incredible. Hoping they achieve it.
 
GregI said:

Zen3 FP IPC Gain ～10%, Int IPC Gain >> 10%. ST perf (Frequency + IPC) Gain 15-20%.

Cinebench R20 Single thread over 600 points if these leaks are correct (can't see why they wouldn't be). According to the Overclockers UK database the rank 1 score for ST CB20 is 601 by a 9900k at 5.7 Ghz.

Zen 3 is basically going to be a 5.75 Ghz 9900k.
Click to expand...

A Zen 3 6 core would score about 4200 MT.

Around 630 ST given the average Zen 2 scores around 530.

Nice...
 
https://wccftech.com/amd-zen-3-ryzen-4000-vermeer-cpus-detailed-up-to-16-cores-32-threads/

Unlike the previous generation design where each CCD comprised of two CCX's (Core Complexes), the Zen 3 CCD will consist of a single CCX which will feature 8 cores that can run in either a single-thread mode (1T) or a two-thread mode (2T) for up to 16 threads per CCX. Since the chip houses a maximum of two CCDs, the core and thread count will max out at 16 cores and 32 threads which is the same as the existing flagship AM4 desktop CPU, the Ryzen 9 3950X.

Each Zen 3 core will feature 512 KB of L2 cache for a total of 4 MB of L2 cache per CCD. That should equal 8 MB of L2 cache on a dual CCD CPU. Along with the L2 cache, each CCD will also comprise of up to 32 MB of shared L3 cache. For Zen 2, the L3 cache was split between the two CCX's with each CCX having their own separate (Up To) 16 MB cache. The size of the cache remains the same per CCD but now all cores can share a larger number of L3 cache.

AMD's Ryzen 4000 'Vermeer" Desktop CPUs with Zen 3 cores will introduce a slightly improved scalable data fabric, supporting up to 512 GB per DRAM channel or up to 1 TB of ECC DRAM. For the memory interface, Ryzen 4000 Desktop CPUs will retain native DDR4-3200 speeds. There will be 2 unified memory controllers on the CPU, each supporting one DRAM channel for a total of 2 DIMMs per channel. The following are the details for the I/O and PCH feature set for the IOD:

Scalable Data Fabric. This provides the data path that connects the compute complexes, the I/O interfaces, and the memory interfaces to each other.

  • Handles request, response, and data traffic
  • Handles probe traffic to facilitate coherency, supporting up to 512GB per DRAM channel
  • Handles interrupt request routing (APIC)
  • Scalable Control Fabric. This provides the data path that provides a configuration access path to all blocks
  • Handles configuration request, response, and data traffic
  • GMI2: Up to two special Data Fabric ports, for connections to the CCDs.
Memory interface

  • 2 Unified Memory Controllers (UMC), each supporting one DRAM channel
  • 2 DDR4 PHYs. Each PHY supports:
  • 64-bit data plus ECC
  • 1 DRAM channel per PHY
  • 2 DIMMs per channel
  • DDR4 transfer rates from 1333MT/s to 3200MT/s
  • UDIMM support
PSP and SMU

  • MP0 (PSP) and MP1 (SMU) microcontrollers
  • This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP).
  • Thermal monitoring
  • Fuses
  • Clock control
NBIO

  • PCI Device ID information uses Vendor ID is 1022h for all devices (see Table 18 [PCI Device ID
    Assignments.].
  • 2 SYSHUBs
  • 1 IOHUB with IOMMU v2.x
  • Two 8x16 PCIe controllers supporting Gen1/Gen2/Gen3/Gen4. Note that SATA Express is supported by combining an x2 PCIe® port and two SATA ports on the same 2 lanes.
  • 24 total lanes combo PHY, UPI muxing
Fusion Controller Hub (FCH or southbridge (SB))

  • ACPI
  • CLKGEN/CGPLL for refclk generation
  • GPIOs (varying number depending on muxing)
  • LPC
  • Real-Time Clock (RTC)
  • SMBus
  • SPI/eSPI
  • Azalia
  • High Definition Audio
  • Up to 2 lanes of SATA Gen1/Gen2/Gen3, also provides the legacy SATA support for SATAe
  • ports. Shared with PCIe
  • SGPIO
  • USB3.1 Gen2
  • 4 ports, includes support for legacy USB speeds
 
Yeah you're right but the most important confirmation not known before was memory speed. Looks like 3600 will still be the sweet spot. I expected them to raise this.
 
GregI said:
Yeah you're right but the most important confirmation not known before was memory speed. Looks like 3600 will still be the sweet spot. I expected them to raise this.
Click to expand...
Eliminating the inter-CCX latency with an 8-core CCX design will give a much bigger performance increase than upping RAM speeds. Now yes, the faster the IF runs, the lower the cross-CCD latency, but you're not having to jump between CCD and IO die anywhere near as much as with Zen 2 because all cores on a chiplet can talk to each other directly. Gross oversimplification I know, but the idea is you're not stacking up as many latency hits with Zen 3 so a faster IF isn't needed.

Note we're talking about native speed here. The improvements to the IF could mean it has a higher ceiling than Zen 2, which means you can clock your RAM faster and still retain 1:1 ratio. If the IF on Zen 3 can reliably hit 1,900MHz or even hit 2GHz then our RAM sweet spot increases. Talk of a 2GHz IF was one of the rumours for why the 3000 XT line even existed, so perhaps that's going into Zen 3.
 
chroniclard said:
Should be a decent bump, im still on a 2700x, though I would also have to upgrade my motherboard and possibly ram. :rolleyes:
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Yeah im going to have to do a full upgrade, only thing i might take over is my 1070 graphics card and my storage but I dont think anything else can come.
 
Participant said:
Zen 3 being named Ryzen 5000 makes a lot of sense to me, to differentiate from the 4k mobile chips.
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Not sure why that would be an issue. It's not like you can drop them into AM4 boards.

Jumping a thousand in the naming scheme would only be required to make sure you don't get compatibility issues with the desktop APUs when AMD switch socket. Right now, the APUs start the new thousand nomeclature off, but they're a generation behind in arch than the desktop CPUs. That in itself isn't a problem, but if 5000 series APUs are the last bastion of AM4 and 5000 CPUs move to AM5, you end up with major confusion because APUs can't drop into the same boards as the CPUs. But even that is solved by just not releasing desktop APUs on the previous socket. So by all means launch the new mobile APUs under 5000, but the desktop APUs hold off until AM5 is ready for the 5000 CPUs.

Now granted you could bump up to 5000 for the CPUs now and launch the next APUs as 5000, but then there's the implication that the APUs are last to the party and obsolete within months, which is not a good look when trying to get more OEM orders. Mobile APUs have to be released "first" in a new thousands series because it comes across as progressive.
 
LePhuronn said:
Not sure why that would be an issue. It's not like you can drop them into AM4 boards.

Jumping a thousand in the naming scheme would only be required to make sure you don't get compatibility issues with the desktop APUs when AMD switch socket. Right now, the APUs start the new thousand nomeclature off, but they're a generation behind in arch than the desktop CPUs. That in itself isn't a problem, but if 5000 series APUs are the last bastion of AM4 and 5000 CPUs move to AM5, you end up with major confusion because APUs can't drop into the same boards as the CPUs. But even that is solved by just not releasing desktop APUs on the previous socket. So by all means launch the new mobile APUs under 5000, but the desktop APUs hold off until AM5 is ready for the 5000 CPUs.

Now granted you could bump up to 5000 for the CPUs now and launch the next APUs as 5000, but then there's the implication that the APUs are last to the party and obsolete within months, which is not a good look when trying to get more OEM orders. Mobile APUs have to be released "first" in a new thousands series because it comes across as progressive.
Click to expand...

AMD want Zen3 to be regarded as completely new ad 'revolutionary' architecture, so obviously they don't want any confusion with Zen2 4000 CPU's and new desktop Zen3 4000 CPU's. This is avoided by moving the desktop to 5000 for total seperation.

AMD's CPU numbering scheme currently doesn't make sense, it's confusing and they need to come up with something more logical.
 
I'm just hoping that brand new Zen3 will finally be able to match, or beat, Intel's 5 year old architecture (Skylake) and almost 6 year old 14nm process in gaming performance (10900k is still Skylake, on 14nm)

My 6700k is coping well with 4K as I'm GPU limited, but when I get a 3080 20GB/3090, or big Navi, I'll likely want to upgrade. Still hoping I can wait it out for LGA1700/AM5 platforms though, as nice to have a big IO upgrade :)
 
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