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AMD far future prototype GPU pictured
- Thread starter LtMatt
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Soldato
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Lol.
Caporegime
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Aside from the fact it's a VERY old story that you just spotted because someone bumped the thread, the more recent info is the interesting part.
Interposers and HBM(high bandwidth memory) are going to be THE killer feature, it's just about time, when the performance/power/cost make it viable. Interposers are being done in tiny quantities(10k-100k a year at immense cost) currently but in the next 6-24 months those numbers are pushing up towards more like 2-20mil a year and the price comes down. Then we'll start seeing more things like on die memory for APU's, insane bandwidth for the gpu and won't be long before we start doing it for discrete gpu's to increase bandwidth.
Memory access is a huge power hog, accessing on die memory takes a fraction of the power it does to access memory on the same package(in the past decade anyway), which takes a fraction of the power it takes to access memory off package like system memory.
On die is stupid expensive because you have a huge amount of space used by memory and that means huge chips and tiny yields. With interposers they are making essentially a very very thin chip with copper interconnects(magnitudes smaller than the pins on a cpu) which enables them to go off die, but maintain the speed and low power. Interposers will mean memory on package but with effectively on die speeds and bandwidth. Stacked memory means they can fit massively more memory on the same package. If you look at the picture of the chip, instead of making a over double sized APU, you make a normal APU and separate memory chips, also meaning dedicated processes, this is insanely lower cost. Then you use an interposer and attach the apu and memory chips to it. But look at the package size, 1-2 memory chips, 256-1gb maybe. More chips means larger and more expensive interposer, more chance for things to fail, lower yields, higher cost. When you can stack the chips you have less connections, smaller interposer and smaller yield hit.
2014-2015 has for maybe 3-4 years been the aim for interposers/stacked memory to become mainstream. The tech, as shown by that picture, was doable on bigger processes and pretty much 3 years ago, but the cost made it entirely not worth it. It's semi what Intel did with Crystalwell, it's the direction both companies are going but it's too low volume to be low cost yet, when it is, everything gets it and it improves chips in every way possible.
Think Kaveri, but 4gb of gddr5 on die, with a 1024bit bandwidth, using half the power as accessing the gddr5 off die would use....... awesome.
Interposers and HBM(high bandwidth memory) are going to be THE killer feature, it's just about time, when the performance/power/cost make it viable. Interposers are being done in tiny quantities(10k-100k a year at immense cost) currently but in the next 6-24 months those numbers are pushing up towards more like 2-20mil a year and the price comes down. Then we'll start seeing more things like on die memory for APU's, insane bandwidth for the gpu and won't be long before we start doing it for discrete gpu's to increase bandwidth.
Memory access is a huge power hog, accessing on die memory takes a fraction of the power it does to access memory on the same package(in the past decade anyway), which takes a fraction of the power it takes to access memory off package like system memory.
On die is stupid expensive because you have a huge amount of space used by memory and that means huge chips and tiny yields. With interposers they are making essentially a very very thin chip with copper interconnects(magnitudes smaller than the pins on a cpu) which enables them to go off die, but maintain the speed and low power. Interposers will mean memory on package but with effectively on die speeds and bandwidth. Stacked memory means they can fit massively more memory on the same package. If you look at the picture of the chip, instead of making a over double sized APU, you make a normal APU and separate memory chips, also meaning dedicated processes, this is insanely lower cost. Then you use an interposer and attach the apu and memory chips to it. But look at the package size, 1-2 memory chips, 256-1gb maybe. More chips means larger and more expensive interposer, more chance for things to fail, lower yields, higher cost. When you can stack the chips you have less connections, smaller interposer and smaller yield hit.
2014-2015 has for maybe 3-4 years been the aim for interposers/stacked memory to become mainstream. The tech, as shown by that picture, was doable on bigger processes and pretty much 3 years ago, but the cost made it entirely not worth it. It's semi what Intel did with Crystalwell, it's the direction both companies are going but it's too low volume to be low cost yet, when it is, everything gets it and it improves chips in every way possible.
Think Kaveri, but 4gb of gddr5 on die, with a 1024bit bandwidth, using half the power as accessing the gddr5 off die would use....... awesome.
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Yep it is old and i should have stated that. Still interesting though.
Caporegime
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^ Lol. Guess i may as well come clean and say i didn't look at the date.
Dm was right. Someone bumped it on twitter i think and i thought it was new.
It's new because someone added info in the thread, basically updated info about it as the picture resurfaced with people talking about that same chip and the tech involved, basically saying it's due in 2014/15.
http://electroiq.com/blog/2013/12/amd-and-hynix-announce-joint-development-of-hbm-memory-stacks/
Basically they've announced a partnership and say 3d chip production is going forward in the next 18 months, it's possible now, and really has been possible for a year or so but it's just too expensive.
AMD/Intel/anyone else can make these kinds of chips as prototypes WAY in advance of production being a real prospect, and then you get some point after volume production becomes possible(in the last year or so) to when production is actually advanced enough for it to be a viable option cost/yield wise. We're getting fairly close for that.
http://www.semiwiki.com/forum/content/3003-amd-goes-3d.html
Essentially Charlie's story is the "this is what they are doing behind closed doors.... in fact closed, padlocked doors, multiple ones, in the secret dungeons, and lol, I got a picture"
The newer info is AMD starting to talk about it publicly as it becomes a real option soon.
Permabanned
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Stacked RAM o.O
That'll be a game changer!!
That'll be a game changer!!
Soldato
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Well Nvidia already said they where going with stacked ram with Volta so this is late 2014 GPU most likely early 2015
Caporegime
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I have posted that on several forums ages ago!! 
Edit!!
Some more recent information:
http://electroiq.com/blog/2013/12/amd-and-hynix-announce-joint-development-of-hbm-memory-stacks/
https://www.semiwiki.com/forum/content/3003-amd-goes-3d.html
Edit!!
Some more recent information:
http://electroiq.com/blog/2013/12/amd-and-hynix-announce-joint-development-of-hbm-memory-stacks/
https://www.semiwiki.com/forum/content/3003-amd-goes-3d.html
Last edited:
Caporegime
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You might want to check my last post,for an update.