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AMD has an 8 core eng. sample, with DDR4 running at 5000mhz+ (1t)

Oops I see it now... Couldn't it just be that the Ring/cache clock is very low because it's an engineering sample.

If the final product's IMC ran at 1:2 (rather than 1:1), Ram clocked at 5000mhz would be pointless.
 
g67575 said:
Oops I see it now... Couldn't it just be that the Ring/cache clock is very low because it's an engineering sample.

If the final product's IMC ran at 1:2 (rather than 1:1), Ram clocked at 5000mhz would be pointless.
Click to expand...

It has nothing to do with it being an engineering sample. It would have been chosen by the user in the bios setup. Almost certainly because it just wouldn't boot at 1:1.
 
I remember now, with AMD CPUs, the infinity cache clock, and memory controller clock are tied together...

Intel has a separate Cache/Ring ratio that can be set.

I see no reason why the cache frequency / IMC clock couldn't be improved for the Zen 3 refresh retail versions, though.
 
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This is why spouting theory with no hands on experience of the platform really doesn't help!

Armchair experts all over these days, just because they watch a few YouTube videos. :p
 
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