TDP is basically a guarantee that the CPU will consume no more power than for example 65w/125w at base clock speed... So, clock speeds above this point will require increasing amounts of power and voltage for each 100mhz (or at least, that is my assumption).
Generally, the unlocked K chips have the highest base clocks.
For the 9th Gen, there's the 8 core 9900KS, with a base clock of 4.0ghz and a tdp of 127w.
For the 10th gen, the 8 core 10700K has a base clock speed of 3.8ghz, tdp = 125w. Also, the 6 core 10600K has a base clock of 4.1ghz, at the same tdp of 125w.
The 11th gen was bad in a lot of ways, but also had lower base clock speeds at a tdp of 125w than the last 2 generations.
For the 12th gen, the 8 P core 12700K has a base clock of 3.6ghz, with a tdp of 125w. The higher spec 8 P core 12900KS has a lower base clock of 3.4ghz at 150w!
That is despite the more advanced, more transistor dense 10nm fabrication technology.
So, am I correct in thinking that the 13th generation is likely to have similarly low base clock speeds, for the same or higher rated tdp?
Is the reason partly due to the generational increases in L3 cache (and L2 in the future)?
Generally, the unlocked K chips have the highest base clocks.
For the 9th Gen, there's the 8 core 9900KS, with a base clock of 4.0ghz and a tdp of 127w.
For the 10th gen, the 8 core 10700K has a base clock speed of 3.8ghz, tdp = 125w. Also, the 6 core 10600K has a base clock of 4.1ghz, at the same tdp of 125w.
The 11th gen was bad in a lot of ways, but also had lower base clock speeds at a tdp of 125w than the last 2 generations.
For the 12th gen, the 8 P core 12700K has a base clock of 3.6ghz, with a tdp of 125w. The higher spec 8 P core 12900KS has a lower base clock of 3.4ghz at 150w!
That is despite the more advanced, more transistor dense 10nm fabrication technology.
So, am I correct in thinking that the 13th generation is likely to have similarly low base clock speeds, for the same or higher rated tdp?
Is the reason partly due to the generational increases in L3 cache (and L2 in the future)?
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