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Conroe's true 64-bit processors ?

I may be wrong, but wasn't sse added to the pentium 3? I thought that was the only difference between the first model pentium 3s and latter model pentium 2s.

On the other hand who started the mhz war, i believe that was AMD with the athlon. Intel had to react as the mainstream market just assume 4ghz = twice as good as 2ghz (not unreasonable when you think about it).
 
utherpendragon said:
I may be wrong, but wasn't sse added to the pentium 3? I thought that was the only difference between the first model pentium 3s and latter model pentium 2s.

On the other hand who started the mhz war, i believe that was AMD with the athlon. Intel had to react as the mainstream market just assume 4ghz = twice as good as 2ghz (not unreasonable when you think about it).

SSE was added to the P3, SSE2 was the P4's party trick (and SSE3 in prescott onwards form)
 
I think you're right (and NathanE, good contribution both of you) about us not agreeing, but there's a couple of things I'm going to have to address....

Vertigo1 said:
The point I'm trying to make is that the Netburst architecture itself was a fundamentally flawed design which brought nothing revolutionary to the table. Please note that I'm making the distinction between Netburst and the other technologies that it may have supported or even given rise to, such as SSE and HT.

Netburst was NOT a fundamentally flawed architechture when the initial assumptions were taken into account. The fact that the assumptions proved false (and by extention the chip design showed flaws) doesn't make it quite as simple as you try to paint it. Intel did not sit there and say "I know, lets make a crap chip that just seems to go really fast." Contrary to what you may believe, they aren't that dumb.

There were two big assumptions that proved seriously false that were made by Intel designers originally.

1) Good code design and optimisation will reduce the impact of increased pipeline length.

This is actually perfectly true, and is frequently used on specific function, deep pipelined chips. A deep pipeline in itself is not a problem, apart from when the pipeline stalls, which can be minimised by optimised code. The problem intel had was that (a) it's optimised compiler produced code that ran great on a P4 and crap on everything else, and therefore wasn't really used, and (b) Trying to optimise code across a PC is nothing like optimsing code on a computing unit trying to do a specific function. A PC is a multipurpose, multifunction device that is frequently performing lots of different, unrelated functions at the same time. Even with each program correctly optimised, you can still end up with serious problems as you cannot optimise the programs to truely work with each other.

2) We should be able to scale this CPU to 10ghz or so.

Obviously, this never happened. Various things foiled this plan, including (1) above, heat problems, manufacturing issues etc etc.
 
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