As you can see I've been doing a few calculations to work out the performance of my motherboard/CPU/memory etc.
I did this for stock and overclocked components. Heres My Findings:
NB: Bus Width x Frequency (MHz) x Transfers Per Cycle = Bandwidth (MB/s)
NB: Frequency (MHz) x Transfers Per Cycle = Effective Clock (MT/s)
STOCK FSB: (1066MT/s FSB)(10.5 Multiplier)(2.8GHz Core Clock)
OVERCLOCKED FSB: (Core Clock = FSB x Multipler) = 3202.5GHz
STOCK MEMORY BUS: (DDR2 PC-6400)(800MT/s) DRAM:FSB Ratio = 12:8 or 3:2
Memory Bus higher bandwidth than FSB? Despite being lower effective clock?
Why is my memory bus higher bandwidth than FSB if they both need to be the same? Even 1066MT/s memory would result in higher bottleneck?
I need some solid information regarding why both bus speeds are different, why they use different bandwidths and why they have different bus widths.
Thanks, I'm Just Into this kind of thing...
Emphacy.
I did this for stock and overclocked components. Heres My Findings:
NB: Bus Width x Frequency (MHz) x Transfers Per Cycle = Bandwidth (MB/s)
NB: Frequency (MHz) x Transfers Per Cycle = Effective Clock (MT/s)
STOCK FSB: (1066MT/s FSB)(10.5 Multiplier)(2.8GHz Core Clock)
- Bus Width: 64BIT (8Byte) Wide Data Bus
- Transfer Rate: Intel AGTL+ (Quad Pumping) 4 Transfers Per Clock Cycle (QDR - Quad Data Rate)
- Bandwidth: CPU FSB = 266MHz = 8Byte x 4 x 266MHz = 8512MB/s
- Effective Clock: 266MHz x Transfers Per Cycle = 1064MT/s (CLOSE TO 1066MT/s)
OVERCLOCKED FSB: (Core Clock = FSB x Multipler) = 3202.5GHz
- Bus Width: 64BIT (8Byte) Wide Data Bus
- Transfer Rate: Intel AGTL+ (Quad Pumping) 4 Transfers Per Clock Cycle (QDR - Quad Data Rate)
- Bandwidth: CPU FSB = 305MHz = 8Byte x 4 x 305MHz = 9760MB/s
- Effective Clock: 305MHz x Transfers Per Cycle = 1220MT/s
STOCK MEMORY BUS: (DDR2 PC-6400)(800MT/s) DRAM:FSB Ratio = 12:8 or 3:2
- Bus Width: 128BIT (16Byte) Wide Data Bus
- Transfer Rate: 2 Transfers Per Clock Cycle
- Bandwidth: DRAM Frequency = 400MHz - 400MHz x 16Byte x 2 = 12800MB/s
- Effective Clock: 400MHz x Transfers Per Cycle = 800MT/s
- Bus Width: 128BIT (16Byte) Wide Data Bus
- Transfer Rate: 2 Transfers Per Clock Cycle
- Bandwidth: DRAM Frequency = 460MHz - 460MHz x 16Byte x 2 = 14720MB/s
- Effective Clock: 460MHz x Transfers Per Cycle = 920MT/s
Memory Bus higher bandwidth than FSB? Despite being lower effective clock?
Why is my memory bus higher bandwidth than FSB if they both need to be the same? Even 1066MT/s memory would result in higher bottleneck?
I need some solid information regarding why both bus speeds are different, why they use different bandwidths and why they have different bus widths.
Thanks, I'm Just Into this kind of thing...
Emphacy.