Intel splits up manufacturing group amid production delays

[kleox64]

I don't see a prediction. I also don't see any content, suggestion or opinion to support the clickbait headline. It's simply rabbiting what we've all been saying since CES.

Fake news, its well known semiaccurate has an issue with Intel.
Like I said before, at these nodes you cant compare the sizes as each manufacturer measures differently, some nodes from the same manufacturer are the same yet they change the size for marketing i.e. Samsung 14LPP vs 11LPP for example, identical process except for changes in some of the metal layers... 11LPP is actually worse performing.

Intel's 14nm++ in terms of density is equivalent to 10nm (TSMC), look at the datasheets/PDK, another thing to note is the validation criteria in terms of noise, cross-talk, EMIR, EM, IR drop etc... is far far stricter on Intel's node to the point its considered overkill.

 

[4K8KW10]

Fake news, its well known semiaccurate has an issue with Intel.

Where did you see S|A at all?
The link is another website with a prediction that Intel could pay the ultimate price under the competitive pressures incoming.

 

[kleox64]

Where did you see S|A at all?
The link is another website with a prediction that Intel could pay the ultimate price under the competitive pressures incoming.

The original rumour is from SA if I remember correctly.

 

[drunkenmaster]

The problem is a lot of people think that because Intel 10nm was a big fat failure that it is a road block to 7nm - but Intel's 7nm is not a refinement or evolution of their 10nm - it started life separately to 10nm with understanding that many of the technical aspects that have stumbled the 10nm development would be issues while they thought they'd get away with it a 10nm. Obviously then there is the whole mismanagement side but that is another story.

Yes, that is the exact same story Intel told everyone with 14nm delays in regards to 10nm, the reality is utter utter bull.

7nm is going to use EUV, but as with everyone else, not for every layer, it's slow and ludicrously expensive and simple equipment supply is an issue and they've also only got plans for a single fab for 7nm so far. It's not financially viable to go all EUV which means many if not most layers being done with quad patterning. The problem there is that it's a fundamental part of the 10nm process. What other things are part of 10nm process, yeah, cobalt usage (something people hype up as new but TSMC have been using since 16nm, the only difference is Intel is using more of it and in different places and a different gate design), gate designs, equipment, yields, etc.

The idea that anyone can simply make 7nm completely separately from another node that uses most of the same technologies is simply absurd, completely and utterly absurd. they worked on them concurrently but every single company is working on technologies for the next several nodes. Intel is talking a big game and it's all bull, it's stock market messaging of their issues. Ignore these delays sure they are bad but the next thing is on track. As said the exact same story they gave for 14nm delays and how 10nm would get them back on track... oops.

All that is really happening is while Intel work on a non EUV 10nm process they are also working on EUV and getting it working ready for 7nm and some other improvements. Every other company is doing the same.

More over if 7nm was 'on track' and was limited by EUV and they had a 2 year lead on the rest of the industry, why are Samsung and TSMC going into production with 7nm EUV and TSMC are starting risk production of 5nm EUV (every bit the match for Intel 7nm) next month while Intel has absolutely zero signs of 7nm coming before 2021 at the earliest (and extremely unlikely imo). If 7nm was being made independently and wasn't effected by 10nm issues, 7nm would have already launched, that's how late 10nm is.

7nm will fundamentally rely on everything that isn't currently working on 10nm and anyone who thinks otherwise is crazy or buying Intel's excuses.

Also as Anandtech's latest article on Intel's claims about 7nm being on track say, well those quote sums it up..

That said, Intel is clearly not skipping any of its already announced 10 nm products, but implies that its 7 nm products may hit the market earlier than we might expect today (i.e., four years after the 10 nm).

Right now Intel has taken so long to go from 14nm to 10nm that their entire process lead has literally disappeared and now gone the other way. Intel 7nm isn't likely to be any better than TSMC 5nm which could have some low volume products out by the end of the year. If the market things 7nm will be the same gap as 10nm took, Intel's stock will crash. Intel is basically lying about the process being made separately because they need the market to believe 7nm isn't 4 years away.

The 7nm team likely is working on mostly different things because ultimately their base assumption is 10nm works and that all their SAQP layers will just work because the process has been out in volume for a while, their only real focus is making EUV work on smaller features for the critical layers done with it.

The reality is it's much worse than the 14nm to 10nm jump, because while they lied about how 14nm delays won't impact 10nm and it's on target (lol), the fact is 10nm uses quad patterning and cobalt while 14nm used double patterning. IE 10nm was a completely different tech, though in reality if you can't make dual patterning work good luck making quad patterning work. However the reality here is that 7nm will use quad patterning DUVL layers, exactly what 10nm uses, 7nm relies on the equipment and 10nm node much more than 10nm relied on 14nm.

 

[Rroff]

Yes, that is the exact same story Intel told everyone with 14nm delays in regards to 10nm, the reality is utter utter bull.

7nm is going to use EUV, but as with everyone else, not for every layer, it's slow and ludicrously expensive and simple equipment supply is an issue and they've also only got plans for a single fab for 7nm so far. It's not financially viable to go all EUV which means many if not most layers being done with quad patterning. The problem there is that it's a fundamental part of the 10nm process. What other things are part of 10nm process, yeah, cobalt usage (something people hype up as new but TSMC have been using since 16nm, the only difference is Intel is using more of it and in different places and a different gate design), gate designs, equipment, yields, etc.

The idea that anyone can simply make 7nm completely separately from another node that uses most of the same technologies is simply absurd, completely and utterly absurd. they worked on them concurrently but every single company is working on technologies for the next several nodes. Intel is talking a big game and it's all bull, it's stock market messaging of their issues. Ignore these delays sure they are bad but the next thing is on track. As said the exact same story they gave for 14nm delays and how 10nm would get them back on track... oops.

All that is really happening is while Intel work on a non EUV 10nm process they are also working on EUV and getting it working ready for 7nm and some other improvements. Every other company is doing the same.

More over if 7nm was 'on track' and was limited by EUV and they had a 2 year lead on the rest of the industry, why are Samsung and TSMC going into production with 7nm EUV and TSMC are starting risk production of 5nm EUV (every bit the match for Intel 7nm) next month while Intel has absolutely zero signs of 7nm coming before 2021 at the earliest (and extremely unlikely imo). If 7nm was being made independently and wasn't effected by 10nm issues, 7nm would have already launched, that's how late 10nm is.

7nm will fundamentally rely on everything that isn't currently working on 10nm and anyone who thinks otherwise is crazy or buying Intel's excuses.

Also as Anandtech's latest article on Intel's claims about 7nm being on track say, well those quote sums it up..



Right now Intel has taken so long to go from 14nm to 10nm that their entire process lead has literally disappeared and now gone the other way. Intel 7nm isn't likely to be any better than TSMC 5nm which could have some low volume products out by the end of the year. If the market things 7nm will be the same gap as 10nm took, Intel's stock will crash. Intel is basically lying about the process being made separately because they need the market to believe 7nm isn't 4 years away.

The 7nm team likely is working on mostly different things because ultimately their base assumption is 10nm works and that all their SAQP layers will just work because the process has been out in volume for a while, their only real focus is making EUV work on smaller features for the critical layers done with it.

The reality is it's much worse than the 14nm to 10nm jump, because while they lied about how 14nm delays won't impact 10nm and it's on target (lol), the fact is 10nm uses quad patterning and cobalt while 14nm used double patterning. IE 10nm was a completely different tech, though in reality if you can't make dual patterning work good luck making quad patterning work. However the reality here is that 7nm will use quad patterning DUVL layers, exactly what 10nm uses, 7nm relies on the equipment and 10nm node much more than 10nm relied on 14nm.

A lot of this seems to be based on information from SA? who've already proved wrong twice about Intel's 10nm...

They are currently moving 4 fabs to 7nm production at significant cost and are the purchasers of the bulk of the EUV scanners made currently the reason their 7nm is behind the likes of TSMC is due to belatedly switching focus to it with all the management issues and a longer delay recognising the issues at 10nm. Their 7nm development is very much separate to 10nm and actually launched before it.

There is an updated version of the article you are basing some information on also https://www.anandtech.com/show/13731/intel-to-expand-production-capacities-at-multiple-fabs

It is more like a 2.5 year delay for high volume production but they should have some capacity online sooner.

EDIT: I don't disagree as to the lies and BS and I'm not claiming they'll deliver "on time" at 7nm but if they don't it won't be because they are reliant on getting 10nm working to deliver on 7nm as some claim.

 

[drunkenmaster]

First off, nothing came from SA, none of SA's articles cover this issue in the slightest, second that 'updated article' doesn't say what you believe it does. It only says 7nm at Fab 42 (same info that has been around for some time) and EXPANSION at three other fabs, it doesn't say 7nm at those fabs, expansion and 7nm are entirely separate things.

Second, yes, 7nm 100% relies on 10nm process, full stop, no arguing no quibbling. Even that article points it out, 7nm relies on DUV and EUV lithography. 10nm is still attempting to get DUV SAQP working right, without it 7nm is dead in it's tracks. 7nm starting before or after is entirely irrelevant because it still fundamentally makes the assumption that SAQP is working from 10nm, 7nm comes after and adds EUV to it, meaning the only thing their 7nm team has to work on is getting EUV working, if they do they have the basis of 7nm working, but it still requires 10nm and DUV quad patterning to be actually working and if it's not working 7nm has nothing to build on top of.

It's the same as saying Nvidia is working on lets say a 3090ti that uses HBM3, their team doens't do anything at all to develop HBM3 but if they made the 3090ti specifically to work with HBM3 with an HBM3 controller and HBM3 isn't ready and working by the time it's ready, it's still dead in the water and completely relies on it being ready.

Also at the moment there is no 'on time' they haven't given any kind of real date for EUV, and EUV has been worked on behind the scenes for 10+ years by all the companies. As said making smaller features with EUV and single/dual patterning for specifically those layers with EUV, is pretty much childsplay compared to actually getting EUV working. It has huge issues in terms of power sources and simply reliability of the light source. With DUV equipment it can last for thousands of hours without starting to create inconsistencies in the light which requires maintenance on the machine which is pretty cheap to do, with EUV the collector needs replacing every few months and costs a bundle to do so, the longer they can get the collector to not effect efficiency/accuracy the more viable the tech has become. The whole thing is insane, dropping tin droplets, hitting it with a prepulse to turn a ball of tin into a different shape, then hitting the now circle shaped piece of time with the full laser pulse to turn it into plasma which is what emits the light... the whole thing is absolutely bat **** crazy difficult. But once you have that light making small features is just laughably easy. Making 7nm features with 13.5nm EUV is ludicrously easy compared to making 10nm features with 193nm DUV. But again EUV is slow... stupid stupid slow. If every layer was actually done with EUV the whole chip would cost 10x as much to produce and take longer to produce, by making only the most critical layers with EUV you can replace 30-40 DUV layers with 10-20 euv layers and the rest still go quad patterning, maybe even a few with dual/triple patterning. You still fundamentally require those technologies to be working or the 10-20 layers of EUV are entirely wasted within a far larger chip.

 

[Distracted]

First off, nothing came from SA, none of SA's articles cover this issue in the slightest, second that 'updated article' doesn't say what you believe it does. It only says 7nm at Fab 42 (same info that has been around for some time) and EXPANSION at three other fabs, it doesn't say 7nm at those fabs, expansion and 7nm are entirely separate things.

Second, yes, 7nm 100% relies on 10nm process, full stop, no arguing no quibbling. Even that article points it out, 7nm relies on DUV and EUV lithography. 10nm is still attempting to get DUV SAQP working right, without it 7nm is dead in it's tracks. 7nm starting before or after is entirely irrelevant because it still fundamentally makes the assumption that SAQP is working from 10nm, 7nm comes after and adds EUV to it, meaning the only thing their 7nm team has to work on is getting EUV working, if they do they have the basis of 7nm working, but it still requires 10nm and DUV quad patterning to be actually working and if it's not working 7nm has nothing to build on top of.

It's the same as saying Nvidia is working on lets say a 3090ti that uses HBM3, their team doens't do anything at all to develop HBM3 but if they made the 3090ti specifically to work with HBM3 with an HBM3 controller and HBM3 isn't ready and working by the time it's ready, it's still dead in the water and completely relies on it being ready.

Also at the moment there is no 'on time' they haven't given any kind of real date for EUV, and EUV has been worked on behind the scenes for 10+ years by all the companies. As said making smaller features with EUV and single/dual patterning for specifically those layers with EUV, is pretty much childsplay compared to actually getting EUV working. It has huge issues in terms of power sources and simply reliability of the light source. With DUV equipment it can last for thousands of hours without starting to create inconsistencies in the light which requires maintenance on the machine which is pretty cheap to do, with EUV the collector needs replacing every few months and costs a bundle to do so, the longer they can get the collector to not effect efficiency/accuracy the more viable the tech has become. The whole thing is insane, dropping tin droplets, hitting it with a prepulse to turn a ball of tin into a different shape, then hitting the now circle shaped piece of time with the full laser pulse to turn it into plasma which is what emits the light... the whole thing is absolutely bat **** crazy difficult. But once you have that light making small features is just laughably easy. Making 7nm features with 13.5nm EUV is ludicrously easy compared to making 10nm features with 193nm DUV. But again EUV is slow... stupid stupid slow. If every layer was actually done with EUV the whole chip would cost 10x as much to produce and take longer to produce, by making only the most critical layers with EUV you can replace 30-40 DUV layers with 10-20 euv layers and the rest still go quad patterning, maybe even a few with dual/triple patterning. You still fundamentally require those technologies to be working or the 10-20 layers of EUV are entirely wasted within a far larger chip.

Do you work in the field or is this something you research while drunk?

Either way, I want to know more.

 

[drunkenmaster]

https://semiengineering.com/why-euv-is-so-difficult/

Research while drunk, this kind of technology absolutely fascinates me. There are loads of other articles. One thing I wanted to clarify is saying EUV is really slow, it is slower than DUV due to how difficult it is to create the 13.5nm wavelength, but it's SO much more accurate that you can get rid of loads of extra layers. So 10 slow layers instead of 20-30 faster layers is still overall faster, a part done EUV chip should take less time than a full DUV chip to get out of the fab due to the reduced number of layers, particularly for the most complex features which would take the most time in DUV. The issue is as above, EUV is so so expensive and needs so much more and extremely costly maintenance that while it would be fantastic to do every layer with EUV and it would make it way faster and much much simpler to design chips, the cost of EUV only production is entirely prohibitive at this time.

THis is why it's still so utterly reliant on 10nm tech, without quad patterned DUV working great the cost of a fab with almost entirely EUV machines would be astronomical and doing all the easier layers using EUV as well increases the load on the EUV equipment meaning more maintenance costs and downtime per chip made the more of a chip is made using EUV. Lets say EUV can do 10k wafer layers before it needs downtime and expensive replacement parts to maintain accuracy, if you do 10 layers per chip in EUV rather than all 50, you obviously get 5 times the chips out and less overall downtime. EUV is going to be game changing for quality of those layers, but is so costly that it has to be used sparingly. Until EUV costs come down way way closer to DUV in terms of equipment and maintenance costs we won't see all EUV chips except in maybe some extremely critical areas, like custom chips for Nasa projects kinda thing, not stick in your home desktop/laptop/phone kind of chip. The actual machines themselves and the enormous power requirements due to the extremely low effective efficiency means the total cost of running a single EUV machien voer DUV is magnitudes higher.

When they get efficiency up, power sources higher and cost lower EUV should entirely replace DUV but we are far away from that today still.

 

[4K8KW10]

https://semiengineering.com/why-euv-is-so-difficult/

Research while drunk, this kind of technology absolutely fascinates me. There are loads of other articles. One thing I wanted to clarify is saying EUV is really slow, it is slower than DUV due to how difficult it is to create the 13.5nm wavelength, but it's SO much more accurate that you can get rid of loads of extra layers. So 10 slow layers instead of 20-30 faster layers is still overall faster, a part done EUV chip should take less time than a full DUV chip to get out of the fab due to the reduced number of layers, particularly for the most complex features which would take the most time in DUV. The issue is as above, EUV is so so expensive and needs so much more and extremely costly maintenance that while it would be fantastic to do every layer with EUV and it would make it way faster and much much simpler to design chips, the cost of EUV only production is entirely prohibitive at this time.

THis is why it's still so utterly reliant on 10nm tech, without quad patterned DUV working great the cost of a fab with almost entirely EUV machines would be astronomical and doing all the easier layers using EUV as well increases the load on the EUV equipment meaning more maintenance costs and downtime per chip made the more of a chip is made using EUV. Lets say EUV can do 10k wafer layers before it needs downtime and expensive replacement parts to maintain accuracy, if you do 10 layers per chip in EUV rather than all 50, you obviously get 5 times the chips out and less overall downtime. EUV is going to be game changing for quality of those layers, but is so costly that it has to be used sparingly. Until EUV costs come down way way closer to DUV in terms of equipment and maintenance costs we won't see all EUV chips except in maybe some extremely critical areas, like custom chips for Nasa projects kinda thing, not stick in your home desktop/laptop/phone kind of chip. The actual machines themselves and the enormous power requirements due to the extremely low effective efficiency means the total cost of running a single EUV machien voer DUV is magnitudes higher.

When they get efficiency up, power sources higher and cost lower EUV should entirely replace DUV but we are far away from that today still.

Thanks for the link, it's quite old now.
I have two questions - is there anything specific why exactly 13.5nm light is chosen or this is just the result of the plasma from the tin droplet? Is tin a requirement or any plasma can be the EUV light source?
Also, CE of only 5% is too low?

 

[Rroff]

Second, yes, 7nm 100% relies on 10nm process, full stop, no arguing no quibbling. Even that article points it out, 7nm relies on DUV and EUV lithography. 10nm is still attempting to get DUV SAQP working right, without it 7nm is dead in it's tracks. 7nm starting before or after is entirely irrelevant because it still fundamentally makes the assumption that SAQP is working from 10nm, 7nm comes after and adds EUV to it, meaning the only thing their 7nm team has to work on is getting EUV working, if they do they have the basis of 7nm working, but it still requires 10nm and DUV quad patterning to be actually working and if it's not working 7nm has nothing to build on top of.

This is wrong.

 

[4K8KW10]

This is wrong.

But intel can't do anything without ASML and ASML are far from being ready.

Now, I begin to understand why intel's 7nm doesn't depend on 10nm.

 

[Rroff]

First off, nothing came from SA, none of SA's articles cover this issue in the slightest, second that 'updated article' doesn't say what you believe it does. It only says 7nm at Fab 42 (same info that has been around for some time) and EXPANSION at three other fabs, it doesn't say 7nm at those fabs, expansion and 7nm are entirely separate things.

It only says expansion in those countries not even fabs per country but the information for what (or rather what it isn't is available).

But intel can't do anything without ASML and ASML are far from being ready.

Now, I begin to understand why intel's 7nm doesn't depend on 10nm.

Look up who has been the main purchaser from ASML so far.

EDIT: I think some posters might be surprised how far back Intel received the first scanner.

 

[drunkenmaster]

This is wrong.

So exactly how are they going to produce the rest of the chip using DUV and quad patterning? Or will you once again just parrot this 7nm doesn't rely on 10nm at all stuff without once providing any kind of logical argument for why that would be true.

Intel 7nm is NOT going to use EUV for every layer, and if it did no one in desktop or most server markets could afford a single chip they made. So keeping that in mind and that they have to produce the rest of the chip with DUV tech how are they going to do that without using technologies which enable their 10nm to work.

 

[Rroff]

So exactly how are they going to produce the rest of the chip using DUV and quad patterning? Or will you once again just parrot this 7nm doesn't rely on 10nm at all stuff without once providing any kind of logical argument for why that would be true.

Intel 7nm is NOT going to use EUV for every layer, and if it did no one in desktop or most server markets could afford a single chip they made. So keeping that in mind and that they have to produce the rest of the chip with DUV tech how are they going to do that without using technologies which enable their 10nm to work.

But DUV isn't the stumbling block on the technical side for 10nm its the parts that some sites bang on about them relaxing which were too ambitious for the lithography, etc.

 

[4K8KW10]

I will repeat my question to you @drunkenmaster . Is tin the requirement or any molecule, be it oxygen, hydrogen, nitrogen, neon, etc gas molecule, can form the plasma?

 

[drunkenmaster]

Look up who has been the main purchaser from ASML so far.

why don't you back up a claim with sources rather than constantly with the eluding to answers. If you think Intel has purchased the most equipment say so, then say how many, then say what it matters and say if they have enough to go into full production.

Maybe mention that of 30 machines expected to ship in 2019, fully 60% of them are going to TSMC, who are starting mass production pretty much this month while Intel have absolutely no guidance to their investors of any impeding EUV node launch within the next 2 years. You need to buy machines to play around with it, that's how that works. How many finalised manufacturing quality rather than beta or testing lower capacity machines they have is incredibly relevant information.

But DUV isn't the stumbling block on the technical side for 10nm its the parts that some sites bang on about them relaxing which were too ambitious for the lithography, etc.

DUV, as in the light source, isn't the stumbling block, but remotely saying what you said seems to underline that you don't really understand what you're talking about because lets be clear on a few things. Intel were not too ambitious, that's an Intel excuse. TSMC and others can do the same metal layers but specifically chose to stay at 40nm metal pitch because copper is still superior at 40nm and it only becomes necessary to use cobalt below 40nm, cobalt is significantly worse than copper at 40nm sizes, copper gets bad so much quicker below 40nm that cobalt becomes better at lower numbers.

Quad patterning is what is making feature sizes like 36nm difficult for Intel and quad patterning is required for 40nm or 36nm using DUV. Saying it's 'not a DUV problem' is crazy, because DUV wavelength requires something more than dual patterning to get below well, depends I thought 64nm metal pitch, Intel did 52nm best on 14nm but some say they also used triple patterning for the most critical layers which would probably mean 52nm using the triple patterning.

Quad pattering is a DUV issue and required to make 10nm work, 7nm will rely on that tech and use they are absolutely a stumbling block for Intel, if it wasn't 10nm would have been out for years already.

 

[Rroff]

why don't you back up a claim with sources rather than constantly with the eluding to answers. If you think Intel has purchased the most equipment say so, then say how many, then say what it matters and say if they have enough to go into full production.

Maybe mention that of 30 machines expected to ship in 2019, fully 60% of them are going to TSMC, who are starting mass production pretty much this month while Intel have absolutely no guidance to their investors of any impeding EUV node launch within the next 2 years. You need to buy machines to play around with it, that's how that works. How many finalised manufacturing quality rather than beta or testing lower capacity machines they have is incredibly relevant information.



DUV, as in the light source, isn't the stumbling block, but remotely saying what you said seems to underline that you don't really understand what you're talking about because lets be clear on a few things. Intel were not too ambitious, that's an Intel excuse. TSMC and others can do the same metal layers but specifically chose to stay at 40nm metal pitch because copper is still superior at 40nm and it only becomes necessary to use cobalt below 40nm, cobalt is significantly worse than copper at 40nm sizes, copper gets bad so much quicker below 40nm that cobalt becomes better at lower numbers.

Quad patterning is what is making feature sizes like 36nm difficult for Intel and quad patterning is required for 40nm or 36nm using DUV. Saying it's 'not a DUV problem' is crazy, because DUV wavelength requires something more than dual patterning to get below well, depends I thought 64nm metal pitch, Intel did 52nm best on 14nm but some say they also used triple patterning for the most critical layers which would probably mean 52nm using the triple patterning.

Quad pattering is a DUV issue and required to make 10nm work, 7nm will rely on that tech and use they are absolutely a stumbling block for Intel, if it wasn't 10nm would have been out for years already.

The problem aspects are the parts that are closer to 7nm (plus) where TSMC, etc. are deploying EUV the rest of the process is far more relaxed - if what you were saying is true why even bother with EUV at all.

Maybe mention that of 30 machines expected to ship in 2019, fully 60% of them are going to TSMC, who are starting mass production pretty much this month while Intel have absolutely no guidance to their investors of any impeding EUV node launch within the next 2 years. You need to buy machines to play around with it, that's how that works. How many finalised manufacturing quality rather than beta or testing lower capacity machines they have is incredibly relevant information.

That is the 2019 allocation it is not the first shipment.

Might have this wrong as I don't have the information to hand but they've already sold something like 19 with 12 going to Intel going back over I think 5 years.

 

[drunkenmaster]

The problem aspects are the parts that are closer to 7nm (plus) where TSMC, etc. are deploying EUV the rest of the process is far more relaxed - if what you were saying is true why even bother with EUV at all.

That is the 2019 allocation it is not the first shipment.

What have the problem parts of the node got to do with anything? The 7nm node won't be particularly good if 20% is done with double the density of their 10nm node and the rest is relaxed not even 10nm to make it more easily done. Did you notice how 14nm finfets on a 20nm beol didn't give them much more than 10% density gain? having the rest of the chip relaxed with a few ultra dense layers isn't going to being much scaling while Intel is claiming another large scaling jump for 7nm.

As for the 'problem parts' of the chip, 99% of everything heard is rumour, in general you can either do quad patterning or you can't. They will need to aggressively go after scaling to make a decent 7nm node. TSMC's 5nm EUV which says it scaled by about 0.5x over 7nm, will obviously be looking to be extremely aggressive with quad patterning on the rest of the chip, not just the EUV layers.

Regardless once again you're saying even if they relax numbers to what TSMC/Samsung are doing on 7nm, they'll still need quad patterning working, that is still 10nm technology, thus you are still saying that they need 10nm to build EUV onto, while claiming they don't. You're arguing in circles.

Do they need quad patterning for the DUV layers for 7nm, yes or no, if yes, do they have quad patterning on 14nm, if no, do they use it on 10nm, if yes, how can you claim 7nm doesn't rely on 10nm technologies?

On the second part, once again, I didn't claim that previous shipments were more for TSMC than Intel, what I asked you, who is claiming that that Intel has had more machines bought, is to provide any source rather than simply elude to this being true and then ask yourself how this matters. If TSMC had 5 machines for testing up to the beginning of the year and Intel had 8, but TSMC is ordering 18 and will go into mass production while Intel only buys itself another 15 machines in 2021... what does having more machines for testing mean, what does it matter? But again, is there any evidence that what you're eluding to is true at all?

 

[Rroff]

in general you can either do quad patterning or you can't.

Usually with these it isn't as simple as a binary can or can't - generally you will get some sucesses but with too low chance to be commercially viable.

 

[4K8KW10]

On the second part, once again, I didn't claim that previous shipments were more for TSMC than Intel, what I asked you, who is claiming that that Intel has had more machines bought, is to provide any source rather than simply elude to this being true and then ask yourself how this matters. If TSMC had 5 machines for testing up to the beginning of the year and Intel had 8, but TSMC is ordering 18 and will go into mass production while Intel only buys itself another 15 machines in 2021... what does having more machines for testing mean, what does it matter? But again, is there any evidence that what you're eluding to is true at all?

I think the link is https://semiengineering.com/why-euv-is-so-difficult/ and https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithography

I read it that Intel got 60% of the EUV machines.

The problem aspects are the parts that are closer to 7nm (plus) where TSMC, etc. are deploying EUV the rest of the process is far more relaxed - if what you were saying is true why even bother with EUV at all.



That is the 2019 allocation it is not the first shipment.

Might have this wrong as I don't have the information to hand but they've already sold something like 19 with 12 going to Intel going back over I think 5 years.