Ivy Bridge to use 3D 22nm transistors

[xsistor]

Is this you?

That's clearly some other guy called xsistor. clearly.

 

[han_solo]

apologies if this has been raised but has anyone thought about or mentioned the application of this 3d tech to GPU's? applicable/useful or not?

 

[KelDG]

So... why are they called 'tri gate transistors'?



Did Apple not used to use RISC?

After looking into this more, to me it looks like marketing spin. The "tri gate" is basically the gate having more surface area (raised or "3d" as intel put it") in contact with the source/drain.

The technology works by having the gate wrapped over the source/drain and also having multiple source/drains passing through the gate. Important - This does not mean more states. They run in parallel, they are either all on or all off, it is simply to increase the surface area onto the gate allowing for a much more clear signal.

 

[drunkenmaster]

apologies if this has been raised but has anyone thought about or mentioned the application of this 3d tech to GPU's? applicable/useful or not?

No, in general terms CPU processes are expensive very high end processes, beyond sticking as small an IGP as you can get away with ondie as Llano/sandy has done its FAR too expensive to make a top end gpu with it. Process's designed for GPU's are essentially cheap processes, they are "bulk" processes and while good are designed for cheapness and being pretty easy to design for as opposed to CPU processes from AMD(glofo now) and Intel which are really very highly designed with cpu over years to get the best working chips possible.


In the future the uber high end tech trickles down to the cheaper processes so we should indeed see this later on in gpu processes but not at the basically here already 28nm and I don't believe at 22nm(though haven't heard anything about it, glofo have more chance of adding Finfets in as glofo will use them in 32nm cpu process and they will also make 20nm bulk processes for GPU's in the future, TSMC don't really do the uber high end stuff, so they won't be as ready to go with it that soon I'd think).

The number of gates, if you wanted to call it that, doesn't change the actual function of the single transistor.

http://www.anandtech.com/show/4313/...nm-3d-trigate-transistors-shipping-in-2h-2011

One of the big things is voltage reduction, leakage reduction, though with Sandybridge they already added VERY effective power gating which AMD is also adding. It basically means instead of using very low power when idle, it uses a ring of transistors around each core to insulate the core entirely, effectively turning the entire thing off completely which is FAR more effective than reducing leakage(at idle).

Sandybridge is actually insanely good for power usage already so I think we'll be hitting diminishing returns there even with great tech, but high end and mobile will be hit in different ways. Atom only goes so low in power(while still being marginally decent, they do have some silly low power ones but they are pitifully slow), so a big jump there will help them a lot as they want to push Atom into smaller mobile devices as growth is so huge in that segment.

In reality, for the high end, 22nm will enable twice the transistor density, as expected, and either higher clock speeds, or a decent voltage drop for the same clock speeds, again this is pretty standard stuff from one process to the next. Idle power on a "turned on" core could be truly brilliant, but on a 95-125W chip, going from 3 of 4 cores turned off and one core at low power using 15W, to using 6-7W isn't really going to change the habits of most high end users in any significant way.

They will likely as usual use the increase in performance of the transistors, half for a 200-300Mhz clock boost, and half for a power drop.

 

[xsistor]

apologies if this has been raised but has anyone thought about or mentioned the application of this 3d tech to GPU's? applicable/useful or not?

The answer to that question is very simple. When you go below 32nm process size it is no longer efficient to design CMOS using planar transistors. It is more efficient to use finFETs or some other multi-gate device.

the consideration is entirely VLSI and has very little to do with architecture. Nothing, in fact. So essentially GPU CPU or whatever else, if you're working with 32nm > process_size > 11nm then you're better off using some multi-gate tech of which finFETs are the more popular (given that you have the capability)... note that GPUs lag CPUs in tech because Intel is leading the industry. When NVIDIA gets there it will look into using finFETs. Intel is calling its tri-gate finFETs their 3d transistors which is more of a marketing ploy (unless they're referring to the TSV 3D or through-silicon via in 3D which they are most likely not).

 

[sanaxe1]

but it would be completely incompatible with all software ever made.

Or i'm being stupid

Quick tell intel before they release the chip and make a grave mistake.

 

[Simple_Steve]

these new 22nm chips have even better gfx in them dont they?

Yeah but these graphics are terrible already, an improvement on terrible isn't that great. I looked at the stats and they looked ok, but in practice sharing the graphics with the CPU results in very low grade graphics. I bought a lappy for my GF assuming it would be able to handle most things she could fathom to throw at it. but it even has trouble with basic things like running multiple video feeds especially on FS.