Lack of SRAM scaling complicates 3nm and smaller CPUs

[Grim5]

As described by the below Toms Hardware article, memory chips used as Cache in CPUs have basically stoped scaling. For example TSMC's next Gen 3nm node only has a 5% improvement over 5nm, Intel's 4 isn't better.

This matters because there is a recent trend of cache amount on CPUs rapidly scaling and the amount of power required and heat output of the memory is also rapidly increasing.

This causes complications for chip design because going forward more and more of desktop CPu space has to be allocated to cache as logic transistors get smaller but cache transistors stay the same size and adding more cache means more power draw and more heat and the alternative is simply having larger CPUs with more Chiplets

TSMC's 3nm Node: No SRAM Scaling Implies More Expensive CPUs and GPUs

Big problems from tiny memory cells.

www.tomshardware.com

 

[andy_mk3]

Isn't this one of the biggest reasons AMD are going with chiplet based designs? RDNA3 has compute on the smaller node that requires it, then the cache is on the older node where it doesn't scale with the new node.

 

[Chuk_Chuk]

Isn't this one of the biggest reasons AMD are going with chiplet based designs? RDNA3 has compute on the smaller node that requires it, then the cache is on the older node where it doesn't scale with the new node.

Yes it is.

Is L4 cache a thing on CPUs? Will see CPUs having some cache off die?

 

[andy_mk3]

L4 cache was on a few Intel CPUs several years ago but that's about it afaik. I'd imagine cache will stay on die due to the latency that would come with it being off die.

 

[Orcvader]

L1 and L2 will stay on die but L3 can work, AMD proved it with V-cache. I would imagine future chips will eventually have V-cache on an older node.