Liquid metal is not all its cracked out to be!

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I am heavily overclocking an Intel i9-7980XE CPU and decided to use liquid metal. I delidded the CPU and am using Der8auer's Direct Die Frame allowing me to put the cold plate of my custom water cooling loop directly on the chip silicon.

The problem is that the silicon die itself is slightly convex at its top. This apparently is a common issue for Skylake-X CPUs (especially the many core ones, as pointed out by no other than Der8auer himself in a video he made on the issue) - the CPU chip itself not being perfectly flat. It is less of an issue with conventional thermal paste, which is much thicker than liquid metal and can be applied as a thick coat to make up for any die/heat-sink/cold-plate warping or imperfections.

With liquid metal though, and I am using Thermal Grizzly Conductanaut, the general recommendation is to apply a thin coat to the silicon and a thin coat to the heat-sink. This accepted approach does not work for me. Only an oval portion of the chip, representing approx. the central 33% of the total area of the top of the die is coming into contact with the perfectly flat top-notch mirror finished cold plate I am using, an Aqua Computer Cuplex Kryos Next Vario with Vision. The periphery of the silicon around this oval center, due to the convexity of the chip (i.e., the ever so slight central bulge), is not coming into contact with the cold plate under tension (regardless of how much tension I place, within reason). I figured this out by leveling the cold plate on the CPU with LM applied, putting a lot of downward force on it, and seeing that only the central 33% of the die had touched the cold plate. This was easily noticeable due to the disturbance of the LM on both the die and the cold plate, forming an oval like fingerprint at the area of actual contact.

The result of applying two thin layers of LM to the CPU die and cold plate, respectively, is that some cores, probably the ones along the periphery of the die, are either not making contact or are making poor contact with the cold plate and jump to the Tj MAX temperature (or close to it) at load. Other cores near by are also extremely hot. There is an almost 60 degree C disparity between properly cooled cores (near the center of the die) and the overheating ones at the farthest point in the periphery.

I have been able to (temporarily?) resolve this issue on my motherboard which is sitting horizontally on a test-bed by applying a much thicker Conductanaut coat to both the die and cold plate. At this point, I see quite a bit of Conductanaut LM pooling on both surfaces, which goes completely against all recommendations for how to apply LM, but the temps are uniform across cores and very very good when mounted. So good in fact, that I am now motherboard VRM temperature limited in my ability to overclock (MB: ASRock Fatal1ty X299 Professional Gaming i9 XE) as I hit over 800 W at the wall, while the CPU cores remain at a temperature of about 65-70 C.

My concern is what will happen when I actually mount the motherboard vertically in a case, after I am done testing, and that the liquid metal will pool over time to the bottom facing edge of the CPU die due to the effects of gravity. This is despite the great surface tension and capillary action between the cold plate and the die keeping the Conductanaut mostly in place. I have protected the CPU PCB with many layers of nail polish so that any spilled over LM will not short out the tiny resistors and caps on the CPU PCB, but as soon as the LM pools and shifts off of the top facing part of the CPU die when the motherboard is mounted vertically, the cores situated at the top of the die will again lose contact with the cold plate and/or make poor contact, and begin to overheat at load. This effect may be very gradual, assuming it happens at all.

How can LM pooling with a thick coat be prevented and/or avoided, short of sanding down the silicon to make it perfectly flat and risking damage to a $2000 CPU (especially over time, as the protective layer at the top of the silicon will be sanded off)? Milling the cold plate (or laser etching it) to make it concave to match the CPU die is pretty much out of the question since this will be a very complicated expensive process and way beyond what I am willing to do to go forward.

I think for as long as I keep the motherboard horizontal, none of this will be an issue, but as soon as I mount it vertically into a case which is the goal, then the problems may start (after some unknown period of time, depending on how slowly the LM flows/transitions to the bottom).

I am left with just an LM solution of some sort, I think. Will the pooling of Conductanaut be an actual issue or will capillary action and the surface tension of the LM be enough to prevent pooling due to gravity over time despite the two thick coats of it applied to the chip die and cold plate, respectively.

Switching to a non-liquid-metal TM results in much worse temperatures - worse on the order of around 20-30 degrees C under load.
 
To be blunt it is probably something the OP has done - Skylake dies are thinner than is often the case with CPUs and easily bend if too much pressure is applied especially while delidding or mounting a heatsink to test. His post shows limited experience of handling these things with quite a bit of talk about applying force.

This is not true of Skylake-X, the dies are thicker than the regular Skylake dies. In fact, if the dies were thinner and were able to bend just a little to conform to the metal cold plate, I wouldn't be having this issue.
 
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I find it funny you are saying its not all its cracked up to be when the problem is the CPU not being flat then go on to say normal TIM is worse ! ;)

Why not put LM in the middle and surround it with normal TIM. Will stop the LM from "pooling" and be thick enough in the edges of the CPU where it dips.

I will most likely not be able to match thickness well with this method and this will result in uneven cooling, once again. With just LM, the excess gets pushed to the edges where it is most needed, assuming that the cold plate is place very level on the die.
 
How much of a thick layer are we talking?

As long as there isn’t enough to cause a drip from the liquid metal itself you will be fine.

Personally I put just enough so it just stops moving to one side when the die is vertical. But have put more on than I have needed on occasion and never ran into an issue.

Surface tension is surprising on it and if anything would experiment with the amount so you can put as little as possible into the die.

I realize that the surface tension is very good, but have read at least one report and seen at least one pic of it pooling when applied in excess. It is hard to state how thick my layer is, other than it is enough to get puddling and then some (on both mating surfaces). I am putting more along the perimeter of the die and cold plate and less in the middle, but still enough to pool everywhere.
 
Concave heatspreaders worsening contact with heatsink base...
Toothpaste between die and heatspreader...
And now non-flat dies?
How are they even doing those? I mean silicon wafers should be pretty darn flat.

This starts looking endemic.
It's like Intel just stopped caring about things.
Let's hope next CEO does better at Intel's helm.

The dies have always been imperfect (I mean we're talking single digit to maybe 30 microns of imperfection). When they were soldered to the IHS (and now with a thick gob of toothpaste), this is not as relevant. When you try to apply two ridiculously thin layers of LM directly between the imperfect die and a perfectly flat well designed cold plate, that's when you run into an issue with die flatness imperfections.
 
Don't see how that thinner substrate of CPU package would make die bend convex:
https://hothardware.com/news/intel-skylake-cpus-are-warping-under-heat-sink-mounting-pressure
https://www.overclock3d.net/news/cp...n_get_damaged_from_cooler_mounting_pressure/1


Flatness of pretty much anything is sure always about measuring accuracy.
But differences should be at level to not make much real difference for heat conduction.
I wonder if there's something in way how Intel mounts die to substrate that's causing it...

Keep in mind that Intel spreads their thermal paste thick and heavy, probably to account for issues with die (and/or IHS) flatness. If I use a thick layer of Kryonaut I eliminate the issue I have, at the expense of some cooling performance (perhaps as much as 20 degrees when we are talking ridiculous loads at the wall outlet i.e., >400 W).

With a thick enough layer of Kryounaut, my cores were thermal throttling and/or hitting instability as temps rose >95C (on some cores). With a thick enough layer of Conductanaut LM, I am being throttled (after about 30-60 seconds) by the motherboard's VRM temps as I hit >800 watts at the wall. This is with a 4.8 GHz overclock at about 1.34 VCore on all 18 cores, btw, running Prime95 (no AVX) hard... Core temps stay at around 65-70 degrees, with far less variation between cores than Kryonaut, which is very VERY good! I am sure temps would be even better with a thinner layer of Conductanaut, but that is not an option unless one's core and cold plate are perfectly or nearly perfectly flat, thus allowing for uniform thickness of the LM application. As far as I can tell, few dies are perfectly flat and probably even fewer cold plates, unless you go over $100 (and German manufactured).

This probably explains why people go through multiple iterations of applying LM thermal paste, before getting good temperatures. They need to find just the right thickness to make sure the entire CPU die is making good contact with the cold plate/heat sink base.
 
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W
helps the LM stick better and a rougher surface has more surface area,
Is this for sure going to increase the conduction of heat from the die to the cold plate, though? Normally, you want both areas to be as smooth as possible for traditional dielectric thermal paste and there is probably a good reason for that.
 
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