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Socket AM2 screws up the DDR-II clock

kchakkar

kchakkar

kchakkar

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Chip can't get the memory clock right


By Theo Valich: Monday 22 May 2006, 17:29

OH BOY. I can't think of many reasons why AMD would not like us to review the Socket AM2 CPU, but this reason could be a killer thing for all the reviews that will land tomorrow. Expect at least one "accidentally-leaked" marketing or sales presentation from Chipzilla where this thing gets blown out of all proportion.

It seems that AMD's memory controller has a bit of a maths problem. It has a habit of downclocking the system memory by a notch or two. Nothing serious, of course, it's just a matter of the fact that the HyperTransport divider is set at "5", and the number it is dividing is 1000. As we all know, 1000MHz is the actual clock of HyperTransport links. So, AMD works at "200" as a base, which is great if you have memory running at 200MHz, 400MHz, 600MHz, 800MHz, 1000MHz, and 1200MHz and so on.

But, if you have "shock-combo" DDR-I/II memory that runs at 333, 533, 667MHz, you could be in a bit of ruff'n'tumble. And just by accident, that DDR-II memory standard has several speed grades, including those at 533 and 667MHz.

continued:
http://www.theinquirer.net/?article=31874
 
A64s have always fudged memory clock speeds on non whole number dividers, so it's no great surprise to be honest.

Jokester
 
Perhaps the creaks are finally starting to show in the concept of on-die memory controllers. I'm glad Intel has stood firm with its no IMC policy.
 
I wouldn't class it as a mistake, as if you know what you're doing you can still get the RAM running at it's right speed, if you balance FSB, multipliers and dividers, which you would be doing if you're overclocking anyway.

If you're not overclocking you won't know the difference between 257Mhz and 266MHz anyway.

Jokester
 
NathanE said:
Perhaps the creaks are finally starting to show in the concept of on-die memory controllers. I'm glad Intel has stood firm with its no IMC policy.
Click to expand...

It comes from a dodgy implementation in the clock speed logic, rather than any inherent problem with on die memory controllers. The equation the chip uses has the same term on the top as well as the bottom of a division. Normally the terms would cancel out to give you the right answer. Just that it works out the top line first and rounds it...

I believe Intel will be using an on die controller on the replacement to LGA775?

Jokester
 
Jokester said:
It comes from a dodgy implementation in the clock speed logic, rather than any inherent problem with on die memory controllers. The equation the chip uses has the same term on the top as well as the bottom of a division. Normally the terms would cancel out to give you the right answer. Just that it works out the top line first and rounds it...

I believe Intel will be using an on die controller on the replacement to LGA775?

Jokester
Click to expand...

which chip have you heard of that uses this or did you mean the itanium, the kentsfield and as far as i know all of intels current roadmapped CPUs do not use IMCs but continue with the current FSB solution.

Give HTT and DDR2 time new implementation there will be fixes i do not doubt!
 
richard smith said:
Ah, so only on their top end chips then, eh? ;)
Click to expand...
I suppose you could interpret it that way ;)

Seriously though, the Itanium makes Intel no money. They use it for long term research and development. Academics like it. That's about it really.
 
Is the available bandwidth much of a concern especially considering there is only a small difference in maximum and calculated speeds? Also latency is what really matters so having the memory controller on the CPU is giving AMD the latency advantage?

In otherwords it'll make little difference and having an IMC is a good thing? :)
 
Intel plan on going to an on-die memory controller sometime in 2008/09 with Nehalem. They have to do this to compete with AMD in the 4+ server space. They just wont be competetive there untill they impliment it.
 
I don't see what the problem is. It's clearly a BIOS issue since it is not auto-detecting and setting dividers properly.

NathanE said:
Perhaps the creaks are finally starting to show in the concept of on-die memory controllers. I'm glad Intel has stood firm with its no IMC policy.
Click to expand...

Yeah, me too. Why bother with faster memory access times? In fact, screw DDR2, lets go back to SD-RAM!

IMC is the way forward and you can be sure that Intel will have it as soon as they have the data buses to match.
 
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