what do the numbers mean ?

1dmf

1dmf

1dmf

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i've never oc'd before and so apologise if i'm asking stupid questions ;)

i've been watching the 10th anniversary results post and someone shows FSB : DRAM 1:1 , Frequency 365.5mhz and say they are using x9 multiplyer.

what does that mean?

is that the CPU is running @ 3.28 ghz , and how do you calculate the memory, if they show 1 : 1 does that mean the memory is running @ 3.28 ghz aswell ?

surely 667mhz memory can't oc that much, i'm guessing i don't understand how all this works.

your help is appreciated. 1DMF
 
1:1 means it's running at the same speed as the front side bus (FSB). The Multiplier is the clock generator for the CPU. It takes the FSB frequency and multiplies it a number of times. In your case it's multiplying it by 9. At 3.28GHz / 9x multi = about 365 MHz. That's your FSB speed. Overclocking is mostly accomplished by increasing the FSB.

The 667 MHz figure is double the actual RAM frequency becasue it's DDR, double data rate, RAM.
 
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ok, but if your running ddr667 @ 1:1 with an fsb of 365.5mhz does that mean your memory is running @ 2 x 365.5? so the OC is clocking the memory @ 731mhz? is that how it works?
 
cool thanks for helping out all seems confusing at first, so oc'ing ddr 667 @ 731 isn't really that impressive @ the end of the day
 
cool - thanks for the great link, very kind of you, i shall watch with interest, probably wont understand it all, but will give me a good basis to ask more questions no doubt. :D
 
Wow - that was a crash course in memory , but i think I got it....

CAS = Delay from issuing read command to getting the data from active row.

tRCD = Delay from issuing activate row command until row can actually be read.

rRP = Delay from issuing deactivate row command before another row can be activated.

tRAS = Total minimum delay from issuing activate row command to issuing deactivate row command.

CR = Delay from issuing chip select to ability to start issuing commands to the chip (ie. activate row, read row, deactivate row)

How do you put that into real world terms ......

if you have a module with 3(CAS)-3(tRCD)-3(tRP)-8(tRAS)

(I've noticed most don't show the T/CR info)

if it's 3 clock cycles from issuing activate row (tRCD) plus 3 clock cycles from issuing read (CAS) plus 3 clock cycles issuing decativate (tRP).

Doesn't that = 9 clock cycles so how can tRAS = 8 ? (and there is a 1 or 2 cycles to add relative to CR at the begining as you need to chip select before anything can be done)

I'm assuming you have to issue a deactivate before finnishing memory access.

so I take it that tRAS is the most important one, because i'm assuming you couldnt have a tRAS lower than the combination of CR+tRCD+CAS+tRP

so the lower you can get the overall tRAS, the lower the other latencies would have to be?

all input appreciated.

Regards,
1DMF
 
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