What is Intel's Reasoning Behind Vdroop ?

paulselhi

paulselhi

paulselhi

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As the processor ramps up it is given less voltage and thus will not be as stable for overclocks, that seems like asking a weightlifter to build himself up then when he is asked to lift heavy we cut his oxygen supply down

No doubt some guru here will give me a sensible reason why this is implemented but here are my befuddled musings :

Without LLC and with vdroop enable the voltage set in BIOS is capped so vdroop is not an overvolt safety net.

Did Intel implement this to put the scares on uninitiated overclockers causing them to raise BIOS voltages that get so high they put the willies up them, drop their overclocks and consider selling their mothers for a high end chip

Is this some altruistic green policy, higher use less volts but then EIST and SpeedStep does all that..green..yeah right the nuclear people are "glowing" with joy over global warming- invest in uranium !!!
 
Or this: http://www.thetechrepository.com/showthread.php?t=126

The first question that may come to mind is why droop voltage at all. Truthfully, in most cases the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output-voltage spike that results from fast load/current demand changes. The magnitude of the spike is proportional to the magnitude of the load swing and the ESR/ESL of the output capacitor(s) selected. By positioning the no-load voltage (VNL) level near the upper specification limit (bound by the Vccmin load line), a larger negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance (RLL), the output voltage under load can be effectively 'level shifted' down so that a larger positive spike can be sustained without crossing the upper specification limit (such as when the system suddenly leaves a heavy load condition). This makes sense as the heavier the CPU loading the smaller the potential negative spike and vice versa for lower CPU loading/positive spikes. The resulting system is one in which the system operation point is bound by Vccmin and Vccmax at all times (although short excursions above Vccmax are allowed by design).
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See Figure 4 of that article.
 
All very interesting reading but in my case i my volts for overclock are 1.392 in cpu-z (4.2 OC)

To get stable with vdroop i need a higher voltage and so swings upwards due to LLC are just as bad as having to use a higher voltage with vdtoop on

And since many high end overclockers use far higher volts than these with good cooling should i be concerned if i am stable with LLC on ?
 
paulselhi said:
All very interesting reading but in my case i my volts for overclock are 1.392 in cpu-z (4.2 OC)

To get stable with vdroop i need a higher voltage and so swings upwards due to LLC are just as bad as having to use a higher voltage with vdtoop on

And since many high end overclockers use far higher volts than these with good cooling should i be concerned if i am stable with LLC on ?
Click to expand...

I see where you are coming from but I think it's the fact that it might require more voltage with LLC enabled to achieve the same OC that causes the real concern:

With Load Line Calibration disabled in BIOS, setting a CPU Voltage VID of 1.38750 resulted in a no-load voltage of about 1.34V and a full-load value of 1.28V. Enabling this feature and lowering the VID to 1.35000V produced a constant CPU supply voltage, regardless of load (or so it seemed), of 1.33V. Setting a lower VID resulted in a blue screen during Windows boot. Idle voltage was relatively unchanged at about 1.33-1.34V but the full-load voltage required increased by 50mV with no benefit. As you might guess, we recommend you leave this option disabled.
Click to expand...
 
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