If you look at Anandtech's launch article here, they have the block diagrams for X670/X670E/B650/B650E which shows you where the USB ports come from relative to the CPU and the chipset.
Generally speaking, if there are no exclusions/sharing listed in the manual then you're usually fine. Chipset connected stuff does share one narrow uplink to the CPU, but realistically you're not going to notice.
Based on the diagram for B650, I think Im alright for PCIe lanes then.
Im going to go for X870 as the following excerpt from Anandtech states for X670
And while this configuration adds more I/O lanes (and thus more I/O bandwidth), it should be noted that all of these I/O lanes are still gated behind the PCIe 4.0 x4 connection going back to the CPU. So the amount of backhaul bandwidth available between the chipsets and the CPU is not any higher than it is on B650. The name of the game here is flexibility; AMD is not designing this platform for lots of sustained, high-speed I/O outside of the CPU-connected x16 PCIe graphics slot and M.2 slots. Rather, it’s designed to have a lot of peripherals attached that are either low bandwidth, or only periodically need high bandwidths.
in addition if AM5 is going through to 2027 and (if) there is one more gen CPU release then I have a better chance of getting X870 updated for next gen then X670 if they want to be really ***p about it
I don't think it is, X670 is 2 x B650 chipsets as it has 2 x Prom21 chips as opposed to 1 on B650 and X870.Only real worthwhile differences between X670 and X870 is more USB4 and Wifi7, Under the hood it's the same chipset.