Ivy Bridge to use 3D 22nm transistors

danzhang16 · 6 May 2011 at 19:23

Just watched that demonstration/ guide video, was fascinating. Also I think I have a man-crush on Mark Bohr. What a lad.

madindehead · 6 May 2011 at 19:46

xsistor said:
yeah and u dont get ppl running around calling FinFETs "3d transistors" in the way intel is calling their trigates. it's basically one more gate channel.
http://www.nd.edu/~gsnider/EE666/666_05/QZhang_FinFET.ppt

Haha true. I think the "3D transistors" is a media way to hype it up really. Whatever you want to call them though, they are pretty damn sexy.

Or maybe I'm the only one who thinks MOSFETs and other MOS devices are cool...

drunkenmaster · 6 May 2011 at 20:02

CAT-THE-FIFTH said:
At higher voltage the improvement over a 32NM planar transistor starts to diminish it seems. AFAIK,all the current Sandy Bridge processors have a VID over 1V. The planar transistors Intel use ATM are produced on a 32NM bulk process.

It would be interesting to see the advantage when compared to planar transistors produced on a 32NM SOI process and AFAIK this is what AMD is using.

its not that it will be more advantageous in low power devices, in the highest speed devices you don't want/can't have a slower transistor, thats why 32nm chips are at 1v+ so the gate delay is minimal. THe main thing this allows is dropping voltage without such a hit to gate delay.

What their 3d gates allow is basically dropping the voltage further than they could have on 22nm, than a "normal" transistor would have allowed with the same gate delay.

It means more for the speeds a overall power usage at lower voltage.

but this is the same every generation, HKMG's, without it leakage would be horrible and power would increase so you'd have to drop voltage/clock speeds to compensate. AS I said earlier pretty much every generation we get a new extra power countering tech which is almost essential as leakage and power problems get worse the closer you put transistors together. Some gen's this seems to be mostly down to blocking the leakage, some gens its about dropping required voltage for the transistor to work, some gens its both.

The term 3D is misleading, but a genius marketing move, people just associate "3d" with good and new tech. Call it HKMGx3 and no one would give a monkeys or take notice. Call it

3d gates

and people just think Intel have done something fantastic they don't really understand but they think it makes their next chip uber fast somehow.

Finfet's(which is essentially what this is afaik?) isn't new, and has been coming for ages to, most future processes at most companies. As for Intel pushing the industry forward, themselves, yes, industry, no. They share very very little of their process tech with anyone else.

CAT-THE-FIFTH · 6 May 2011 at 20:20

drunkenmaster said:
its not that it will be more advantageous in low power devices, in the highest speed devices you don't want/can't have a slower transistor, thats why 32nm chips are at 1v+ so the gate delay is minimal. THe main thing this allows is dropping voltage without such a hit to gate delay.

What their 3d gates allow is basically dropping the voltage further than they could have on 22nm, than a "normal" transistor would have allowed with the same gate delay.

It means more for the speeds a overall power usage at lower voltage.

but this is the same every generation, HKMG's, without it leakage would be horrible and power would increase so you'd have to drop voltage/clock speeds to compensate. AS I said earlier pretty much every generation we get a new extra power countering tech which is almost essential as leakage and power problems get worse the closer you put transistors together. Some gen's this seems to be mostly down to blocking the leakage, some gens its about dropping required voltage for the transistor to work, some gens its both.

The term 3D is misleading, but a genius marketing move, people just associate "3d" with good and new tech. Call it HKMGx3 and no one would give a monkeys or take notice. Call it

3d gates

and people just think Intel have done something fantastic they don't really understand but they think it makes their next chip uber fast somehow.

Finfet's(which is essentially what this is afaik?) isn't new, and has been coming for ages to, most future processes at most companies. As for Intel pushing the industry forward, themselves, yes, industry, no. They share very very little of their process tech with anyone else.

Yet you are getting chants of AMD is doomed since they are still at 32NM,etc.

However,they are not using the same 32NM technology as Intel so how can people compare the theoretical advantage over what AMD will be using??

On top of this where is the chart detailing 22NM planer transistors versus 22NM finfets??

AFAIK,the current Core i5 processors such as the i5 2500K have a VID of between 1.1V to 1.2V. So either you are looking to push similar clocks at a lower voltage or higher clocks for a similar voltage. At 1.0V the 22NM finfets have an 18% improvement in gate delay as opposed to a 37% improvement at 0.7V.

It would have been interesting to see how much of a difference between the existing 32NM Intel transistors and the 22NM ones at between 1.1V to 1.2V as well.

panyan · 6 May 2011 at 20:45

drunkenmaster said:
There's pretty much a new fancy name for whatever new method they bring in every gen.

i agree, every new generation has some "killer selling point" which is usually just an enhanced version of a tech we have had for ages with a new fancy name

scubes · 6 May 2011 at 20:52

when are these out?

xsistor · 7 May 2011 at 00:59

drunkenmaster said:
Finfet's(which is essentially what this is afaik?) isn't new, and has been coming for ages to, most future processes at most companies. As for Intel pushing the industry forward, themselves, yes, industry, no. They share very very little of their process tech with anyone else.

FinFETs are very similar to trigate FETs but have dual gates. ppl expected nanoelectronics to get here at sub-0.1 microns tech (100nm), but that didn't happen. Engineers found ways of keeping microelectronics tech alive even at sub 0.1 micron process size. But nanoelectronics is inevitable at sub-11nm. Till we get there multi-terminal transistors (esp multi-gate ones) has helped keep microelectronic tech "current" (no pun intended).

But I find it disingenuous of Intel the way they're using this. It's certainly true that at 22nm the thinness of the channels causes a bunch of problems. FD/FinFET type devices, including Trigates, seems the way forward.
And Multi-gate transistors have been there from the beginning.
the new ones are certainly novel and have their place. MuGFETs for example -- though they have gate-source/gate-drain parasitic capacitance issues. Trigates on the other hand have low Rds and parasitic capacitance
there have been devices with as many as 5 terminals for ages.
Or say, GaaFETs, which can have as many as 4 gates. should be calling those 4D transistors then. There have also been 4-5 gate devices going decades back.

5D transistors, as it were...

panyan said:
i agree, every new generation has some "killer selling point" which is usually just an enhanced version of a tech we have had for ages with a new fancy name

The funny thing is I dont see their name catching on among anyone in physics or engineering

then again maybe there referring to the through-silicon vias (TSV 3-D) and not the trigate transistors themselves.

anyway, manufacturing FinFETs is difficult so if they've perfected it good for them

PermaBanned · 7 May 2011 at 01:33

If a transistor is '3D', does that mean it has three gates? As opposed to the traditional two? Because how i see it, a CPU based on transistors with three gates would require a huge rethink of all programming... ever. Binary code wouldn't work, you'd have to come up with a number system of base three and whole new programming languages to control that - not only would it take longer to process with three options but it would be completely incompatible with all software ever made.

Or i'm being stupid, one of the two

MikeHunt79 · 7 May 2011 at 03:25

Superewza said:
If a transistor is '3D', does that mean it has three gates? As opposed to the traditional two? Because how i see it, a CPU based on transistors with three gates would require a huge rethink of all programming... ever. Binary code wouldn't work, you'd have to come up with a number system of base three and whole new programming languages to control that - not only would it take longer to process with three options but it would be completely incompatible with all software ever made.

Or i'm being stupid, one of the two

A lot of this thread is over my head, but I'm guessing normal 2d chips are a single layer, like a single layer PCB, and these new-fangled 3d chips will be multi-layer, like a multilayer PCB, allowing more complex stuff to go on in a limited space... They'll still be sticking with binary, as having 0,1,2 instead of 0,1 would indeed be a rather large change!

xsistor · 7 May 2011 at 04:48

Superewza said:
If a transistor is '3D', does that mean it has three gates? As opposed to the traditional two? Because how i see it, a CPU based on transistors with three gates would require a huge rethink of all programming... ever. Binary code wouldn't work, you'd have to come up with a number system of base three and whole new programming languages to control that - not only would it take longer to process with three options but it would be completely incompatible with all software ever made.

Or i'm being stupid, one of the two

No, no it has absolutely nothing to do with programming. the processor will still work just the same as any other processor. these are very low-level electronic considerations and lie well below programming models and even below processor architecture. as u make chips smaller depletion-layer width becomes comparable in size to channel length and this causes a number of issues. to combat it u need to use vertical transistor design instead of planar transistors and have multi-gates.

PermaBanned · 7 May 2011 at 11:50

But surely in having multiple gates you make it incompatible with the on-off binary code? That or use them in some specific part of the die that doesn't receive programming, in which case they wouldn't make much difference and it's all a gimick anyway?

Shayper · 7 May 2011 at 12:45

Superewza said:
But surely in having multiple gates you make it incompatible with the on-off binary code? That or use them in some specific part of the die that doesn't receive programming, in which case they wouldn't make much difference and it's all a gimick anyway?

I would guess that you switch between channels for each on-off, rather than have each gate as an on off. Therefore you could theoretically do two switches for every regular transistor switch?

I am probably wrong, I am still learning all this stuff!

Paracelsus · 7 May 2011 at 14:39

It doesn't have three gates - still just one - so no problem with binary. The 3D is just referring to the shape of it.

Tediore · 7 May 2011 at 16:16

This was on the news the other night. Depending on performance figures it might tempt me to upgrade from my i5 760 early

Judgeneo · 7 May 2011 at 16:32

At the high end that we all know and love, these won't be that much better than a normal drop in process size. The big advantage is at the low end.

The RISC instruction set that ARM uses to power your phone is much more efficient that the CISC instruction set that powers your Laptop/PC. If Intel want to compete in this game, and they do, then they can only be successful with big power improvements such as this.
I had more or less discounted intel from the mobile race, but this changes things somewhat

PermaBanned · 7 May 2011 at 18:59

Paracelsus said:
It doesn't have three gates - still just one - so no problem with binary. The 3D is just referring to the shape of it.

So... why are they called 'tri gate transistors'?

Judgeneo said:
At the high end that we all know and love, these won't be that much better than a normal drop in process size. The big advantage is at the low end.

The RISC instruction set that ARM uses to power your phone is much more efficient that the CISC instruction set that powers your Laptop/PC. If Intel want to compete in this game, and they do, then they can only be successful with big power improvements such as this.
I had more or less discounted intel from the mobile race, but this changes things somewhat

Did Apple not used to use RISC?

xsistor · 7 May 2011 at 20:13

Shayper said:
I would guess that you switch between channels for each on-off, rather than have each gate as an on off. Therefore you could theoretically do two switches for every regular transistor switch?

I am probably wrong, I am still learning all this stuff!

Superewza said:
But surely in having multiple gates you make it incompatible with the on-off binary code? That or use them in some specific part of the die that doesn't receive programming, in which case they wouldn't make much difference and it's all a gimick anyway?

1. there is no on/off in transistors. That's a simplifcation of actual transistor behaviour which is a current (or voltage) amplifier. This simplification is used to implement digital designs but u dont just end it there because actual transistor behaviour is a lot more complex.
2. You use the multi-gate design to achieve the same result as planar single-gate CMOS but at small process size like 22nm. Having two gates does not equal having two on/off switches (which becomes more apparent when you consider point 1) above. In the ideal multi-gate transistor electrons in one gate affects the behaviour of the other in a similar fashion... actual transistors behave as an approximation of this because they are actually analogue amplifiers and not digital on/off switches.)
3. When designing CMOS circuits there are so many levels. Behavioural modelling is at the top. At the bottom where an HDL is still used, you only get as far as designing transistors using some abstract notion of what NMOS and PMOS transistors will behave like. You don't use AND/OR/NOT etc gates in CMOS design like you do with BJTs but instead you just directly use NType and PType FETs themselves (this is because NType+PType easily reduce to lower complexity than any single AND/OR/NOT gate for the same circuit).
4. It's at below this level that the actual structure of the transistor is considered -- and this is where you normally work in something like 0.1 microns or 0.045microns or whatever. Usually you design transistors at this level and then construct standard cells that have some kind of expected digital behaviour. You then use groupings of these to produce the type of digital behaviour you want.

WingZero30 · 7 May 2011 at 20:57

xsistor would these happen to relate to you judging by your biography?

http://www.youtube.com/user/xsistor

http://thepriorart.wordpress.com/about/

:cool:

xsistor · 8 May 2011 at 00:11

WingZero30 said:
xsistor would these happen to relate to you judging by your biography?

haha why, are u trying to dig up dirt on me?

that's some old stuff, mostly from when i was young and foolish. swarms are still cool, tho

Gtiracer · 8 May 2011 at 07:17

xsistor said:
haha why, are u trying to dig up dirt on me?

that's some old stuff, mostly from when i was young and foolish. swarms are still cool, tho

Is this you?

The name ‘Xsistor’ is a portmanteau word, combining ‘x’ as used in mathematics – the unknown variable – with ‘sistor’ derived loosely from the names of various fundamental electronic devices such as resistors, varistors, capacitors, inductors, thyristors, and transistors.