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AMD Zen 6 rumours

I believe that Zen 6 is still on AM5. It all seems rather expensive to me. The current cpu's are too expensive as it is so we don't need it getting any more expensive.
 
pastymuncher said:
I believe that Zen 6 is still on AM5. It all seems rather expensive to me. The current cpu's are too expensive as it is so we don't need it getting any more expensive.
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I think AMD's high end (none 3D) chips offer the best value. The mid and low end seem to offer a lot less value. Intel mid and low end seem a lot better. I would never buy a 3D version as it offers very little benefit for me at a lot higher price.
 
FredFlint said:
AMD's big-little is different, all the cores support the same instructions, the only difference is power, cache and design density. This should make it simpler to manage(in software), maybe...
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Intel's big littles also have a common instruction set. It's the only way Big Little can work on current operating systems. That's why the big cores had AVX-512 turned off.
 
Nutty667 said:
Intel's big littles also have a common instruction set. It's the only way Big Little can work on current operating systems. That's why the big cores had AVX-512 turned off.
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They are not the same implementation. The AMD "little cores" are the same basic design but built with high density libraries and less cache. The Core IPC is the same, but the difference in performance is due to the different amount of cache and lower clockspeeds. This is why they are called Zen4c and Zen5c.

The Intel design uses two different cores,which are not closely related to each other.
 
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CAT-THE-FIFTH said:
They are not the same implementation. The AMD "little cores" are the same basic design but built with high density libraries and less cache. The Core IPC is the same, but the difference in performance is due to the different amount of cache and lower clockspeeds. This is why they are called Zen4c and Zen5c.

The Intel design uses two different cores,which are not closely related to each other.
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I never said they were.
 
AMD announces Zen6 will be built on TSMC 2nm, has taped out and is ready for launch in 2026

Also, they announced Zen5 EPYC chips are now being built at Arizona, same day Nvidia announced TSMC at Arizona is now also building its Blackwell chips

wccftech.com

AMD Confirms Next-Gen EPYC Venice "Zen 6" CPUs Are The First HPC Product Made Using TSMC's 2nm "N2" Process, 5th Gen EPYC Validated At TSMC Arizona

AMD has confirmed that its next-gen EPYC Venice CPUs, based on the Zen 6 architecture, are made on TSMC's bleeding edge 2nm process node, N2.
wccftech.com wccftech.com
 
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they announce that in the context of the venice server products.
given recent MLID rumours that the Zen6 [family] of products will release across a variety of nodes, i wonder what that means for the release date product we're interested in; Zen6 AM5 desktop?
 
jigger said:
Erm yeah, that’s some really interesting opinions. Intel has very much got its act together in every market that matters.
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Not in every tech that matters though.... They still dont have decent interconnect tech that comes close to infinity fabric. I make them almost 10 years behind in interconnect tech.
 
Vince said:
So what your saying is they are on par in everything but their core markets? So Server, Desktop etc they are behind but they are broadly comparable on Mobile?
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The interconnect issues are largely resolved in majority of Intels professional parts. The traditional CPU performance aspect of mobile parts are quickly becoming less important. The focus is the overall APU performance and power use.

Outside of the desktop market Intel still have to improve, but are in much better shape compared to desktop where Intel are a long way off.
 
jigger said:
The interconnect issues are largely resolved in majority of Intels professional parts. The traditional CPU performance aspect of mobile parts are quickly becoming less important. The focus is the overall APU performance and power use.

Outside of the desktop market Intel still have to improve, but are in much better shape compared to desktop where Intel are a long way off.
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What interconnect are they even using... so many have come and gone... EMIB, Foveros, now DMI... or something else. Just scraping around trying to replicate the magic glue lol.
 
Vince said:
What interconnect are they even using... so many have come and gone... EMIB, Foveros, now DMI... or something else. Just scraping around trying to replicate the magic glue lol.
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lol, def needs more glue, I’m just not sure Intel understood the glue is not for sniffing. Mesh for the E cores parts and ring for the P. Although I’ve heard people describe the bus on the P core chips as a ring of rings. I’m talking about the later Xeons where Intel have P or E core options.
 
jigger said:
lol, def needs more glue, I’m just not sure Intel understood the glue is not for sniffing. Mesh for the E cores parts and ring for the P. Although I’ve heard people describe the bus on the P core chips as a ring of rings. I’m talking about the later Xeons where Intel have P or E core options.
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They really don't.

Analogue (cache, IO, memory links, ecte..) hasn't shrunk with better nodes since 7nm, possibly even 14nm, so rather than that taking up more and more of the die space AMD designed chips that move much of that off the the bit with the cores creating separate chips for analogue and logic.

Aside from that avoiding making the chips larger than they need to be it has two other benefits, you can make the IO die on an older cheap node and it doesn't make the blindest bit of difference, the third benefit is you can assemble the CPU's like Lego, you can scale them from 1 cores CCD to currently 24 using one and the same CCD from the lowest end retail chip to the highest end server chip.

Its the perfect packaging solution, it doesn't get any better and its genius.

Intel are still trying to stitch multiple full CPU's together, you know, like the Pentium D pictured below, this was Intel's response to AMD making the first X86 Dual Core, AMD's was integrated cores as they are today and Intel's response was to 'Glue' two Pentium's together, it didn't work, Intel soon adopted AMD's architecture as we know it today.

etLalFu.jpeg
 
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humbug said:
They really don't.

Analogue (cache, IO, memory links, ecte..) hasn't shrunk with better nodes since 7nm, possibly even 14nm, so rather than that taking up more and more of the die space AMD designed chips that move much of that off the the bit with the cores creating separate chips for analogue and logic.

Aside from that avoiding making the chips larger than they need to be it has two other benefits, you can make the IO die on an older cheap node and it doesn't make the blindest bit of difference, the third benefit is you can assemble the CPU's like Lego, you can scale them from 1 cores CCD to currently 24 using one and the same CCD from the lowest end retail chip to the highest end server chip.

Its the perfect packaging solution, it doesn't get any better and its genius.

Intel are still trying to stitch multiple full CPU's together, you know, like the Pentium D pictured below, this was Intel's response to AMD making the first X86 Dual Core, AMD's was integrated cores as they are today and Intel's response was to 'Glue' two Pentium's together, it didn't work, Intel soon adopted AMD's architecture as we know it today.

etLalFu.jpeg
Click to expand...

Again, outside of desktops Intel have a different approach. Scaling is far less of an issue.
 
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