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AMD Zen 6 rumours

MyBrainz said:
wccftech.com

AMD's Next-Gen Ryzen Zen 6 "Medusa Ridge" CPUs To Come In 12, 24 & 32 Core Flavors, Up To 128 MB L3 Cache

AMD's next-generation Ryzen CPUs based on the Zen 6 core "Medusa Ridge" architecture will pack increased core and cache counts.
wccftech.com wccftech.com

Wonder if Zen 6 will be numbered as 10xxx or will they begin a different numbering scheme.
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If rumors are true and the top model has more than 16 cores, they need to rethink numbering anyway.
threadripper naming tries to stick to same pattern for 24, 32, 64, 96 cores, but it is inconsistent and not immediately obvious


JUST PUT NUMBER OF CORES IN THE MODEL NAME!
Like early Core used D for 2 and Q for 4 and you immediately knew without looking it up.
 
rumours of big cache sizes even on the non-X3D chips and also 12 core ccd's.
Could be huge if true, but a long way away. I would say late 2026 or perhaps even early 2027
 
It would be easier for them and us if they scrap the non X3D ones, and just keep the X3D now that the clock speed difference is pretty much solved. if they can produce them for a similar price and they can make them quickly then I don't see why not.

Definitely is time for the core count per CCD to increase. If they can do 12 or even 16 per CCD without any comprises then that would be great.
 
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Rob_B said:
That's the problem, Vcache is expensive and takes time. I don't see it being the default for a long time.
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I think AMD will end up putting all the L3 under the CCD at some point. It would reduce the size of the CCD by > 20% and reduce the cost of each CCD, just need the stacking costs to go down to make it viable.
 
Raiden85 said:
It would be easier for them and us if they scrap the non X3D ones, and just keep the X3D now that the clock speed difference is pretty much solved. if they can produce them for a similar price and they can make them quickly then I don't see why not.

Definitely is time for the core count per CCD to increase. If they can do 12 or even 16 per CCD without any comprises then that would be great.
Click to expand...

Completely agree, doesn’t seem like there’s any reason to keep the non-X3D models around and the 3D vcache just becomes a standard feature across all models

Ive seen rumours of it being a 12 core CCD’s from zen6 onwards which would be fantastic

Probably about time we had core count increases now
 
From a business production point of view streamlining the lineup to all just be X3D would be nice, but X3D is only useful for gamers and very niche scenario's.
There will be many many more customers wanting a cheaper alternative and it wouldn't make sense for AMD to price themselves out of that market area.
It may just be that production can be streamlined and dummy X3D wafers put down so the automation stream can be as 'simple' as possible rather than having multiple lineups for X3D and non-X3D thereby keeping production costs sensible.

12 core CCD's would be interesting as it would lift up the bottom end of computing....I can't imagine them getting that many core failures to need to create less than a 6core CPU from a 12 core CCD design.
 
I'd rather they keep the non X3D lineup as someone who mostly games who's on a 13600K with DDR4 I was looking at moving to DDR5 and could sidegrade to AM5 with the potential to move to zen6 rather then move to a DDR5 LGA 1700 with no upgrade path.
 
G J said:
I'd rather they keep the non X3D lineup as someone who mostly games who's on a 13600K with DDR4 I was looking at moving to DDR5 and could sidegrade to AM5 with the potential to move to zen6 rather then move to a DDR5 LGA 1700 with no upgrade path.
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I dont see the point in having non-x variants, x ones and then x3d. They’re too similar and seems a waste of resources

Like whats the logic in having a 10800, 10800X and a 10800X3D?
 
Trying not to sound too arsey with this comment but they offer different produicts at different price points for different use cases so that's why they do it.

X3D is too expensive and can hurt performance to add to every chip. Not every chip can become an 'X' maybe due to bad cores not hitting performance/power/speed targets so that gives you your 3 tiers.
 
AMD are not messing about with Zen 6 :eek:

Olympic Ridge:

2X 12 Core CCD + 2LP Zen 5 cores in IO die for a total of 26 cores.
Bleeding edge TSMC N2X, AMD are skipping All N4 and all N3 going straight for the best version of N2.
Much improved faster IO Die to CCD and CCD to CCD transfer links
10% + higher IPC
6Ghz + clock speeds
Have the ability to double stack 3D cache, so the 3D L3 cache amount can go from 96MB currently Zen 5 (9800X3D) to 160MB Zen 6, its currently unknown if this will make it to consumer Desktop, are likely for server, my personal opinion is this is true for Zen 5, 4 and 3 before and they did come to desktop so IMO yes!

Medusa Halo:

24+2 Core
48 RDNA 4.5 CU's
384Bit LPDDR6

Medusa Large:

12+2 core
16 RDNA 4 CU's
128Bit LPDDR5X

Medusa:

4+2 Core
4 RDNA 4 CU's
128Bit LPDDR5X

Bumblebee:
2X Zen 6, 2X Zen 6C, 2X Zen 5 LP.
4 RDNA 3.5 CU's

There is also a 10 watt ARM chip in the works.

AMD really smell Intel's blood now and are homing in on them.

 
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Not sure about the smelling blood bit, Intel is already dead when it comes to sales figures

2nm means it's a while away, TSMC has only just opened orders for 2nm and it's so expensive that even Apple has announced it won't be jumping on 2nm till 2026. Apple used to be known for always moving to the best node as soon as it was available but they are skipping it this year to wait for costs to come down, a company that makes insane margins on its products..

As for 3d cache on each CCX, not happening for gaming chips.

Extra cores plus 10% IPC and 6ghz all core clocks would mean a 10950x is about 60% faster than the 9950x in multithread. I'm glad I skipped 9000 series!

Intel will have its own large gains though, that's why amd is going hard now with extra cores and an advanced node as Intel is also looking a large core count increase for its next gen chips
 
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Grim5 said:
2nm means it's a while away
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With Zen5X3D clearly on top, AMD is confident enough to leave a gap in release. Wait for best node, get best clocks. Possibly get 2 layers of cache.
Intel could release 2 gens in the same time, just to beat Zen 5. And then get hit by Zen 6 train.

Interesting how many different chip designs will exist in parallel. Quite a step away from servers and desktop using exact same identical chiplets.
 
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So AMD finally joining the Big-little architecture. Personally I'm not a fan of that design.
But at least they're keeping the balance the right way around with mostly Big cores and a couple of low power ones for background things, rather than Intel's stuff it with low powered cores.
 
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Nutty667 said:
So AMD finally joining the Big-little architecture. Personally I'm not a fan of that design.
But at least they're keeping the balance the right way around with mostly Big cores and a couple of low power ones for background things, rather than Intel's stuff it with low powered cores.
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AMD's big-little is different, all the cores support the same instructions, the only difference is power, cache and design density. This should make it simpler to manage(in software), maybe...
 
Nutty667 said:
So AMD finally joining the Big-little architecture. Personally I'm not a fan of that design.
But at least they're keeping the balance the right way around with mostly Big cores and a couple of low power ones for background things, rather than Intel's stuff it with low powered cores.
Click to expand...

Doesn't look the same to me when it's mainly performance cores I like this approach
 
Nutty667 said:
So AMD finally joining the Big-little architecture. Personally I'm not a fan of that design.
But at least they're keeping the balance the right way around with mostly Big cores and a couple of low power ones for background things, rather than Intel's stuff it with low powered cores.
Click to expand...
Unlike Intel, AMD's big and little cores are still based on the same architecture. The "c" cores pretty much perform the same as the full core if they were clocked at the same clock speed, only difference is prioritising power and space. It's a lot more easier for the Windows scheduler to handle in this case since all it has to know is which cores are the higher boost cores (which it already has been doing for years).
 
@Grim5 Double stacked as it one on top of the other, so one CCD will have two 3D stacked cache chip's brining the L3 Cache from currently 96MB to 160MB.

Also, H2 2026 for Zen 6.
 
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humbug said:
@Grim5 Double stacked as it one on top of the other, so one CCD will have two 3D stacked cache chip's brining the L3 Cache from currently 96MB to 160MB.

Also, H2 2026 for Zen 6.
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Ah ok that makes more sense

A 10800x3d with 6ghz clocks, 12 big cores on single CCX and double stacked 3d cache, that would be peak for gaming

Though I do expect AMD will be testing the cost-benefit of double stacked cache for consumer parts and if it turns out the double cache doesn't do much more for gaming they may leave it out of consumer desktop parts to cut cost so we'll have to wait and see
 
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