I lol'd when I read this on OC.net about the slides
FLCLimax said:LMAO! Did Zornyan make those slides?
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FLCLimax said:LMAO! Did Zornyan make those slides?
I lol'd when I read this on OC.net about the slides
I'm looking forward to Threadripper reviews; especially with PcPer doing core-core latency tests. I want to see how well two modules with 2 CCXs each copes with latency. Along with what memory frequencies the platform will hit on launch. I'd say launch with 3200Mhz Quad Channel would be fantastic for them if they can manage it; especially in gaming tests.
There are 3 SKUs below the 1920X (two 10c, one 12c) but there are also 4 SKUs between those two, spread over a $200 range. So we may still see a $600-650 entry-level part.
I'm hoping for a decent 10-12 core with great base clocks and also 4-4.1Ghz Boost. Means less reason to bother overclocking.
Hoping the Noctua air coolers also launch same time so we can get rolling right away if these are good.
Well that'll be for 1-2 cores, there likely won't be a SKU any money which will clock above 3.6-3.7 All-core load. Need to overclock for that.
I lol'd when I read this on OC.net about the slides
https://www.bit-tech.net/news/tech/cpus/intel-badmouths-amds-epyc-design/1/
Intel are already on the attack, slating the way the cores work together , but neglecting to mention the `mesh` system their SLX uses , that requires the same optimisations
Except from an optimisation point of view the Intel solution is worse/more limited.
With the Intel solution EVERY core talking to ANY core has high latency, and this latency isn't reduced by RAM speed (or not much anyway).
With the AMD solution talking within a 4-core CCX has VERY low latency (like Skylake-non-X level), and then only crossing CCX boundary has high latency (a bit above Skylake-X). And this latency is also reduced dramatically as RAM clockspeed increases.
So there's clearly more room for improvements and clever code solutions with AMDs approach. E.g. running many instances of a program, but limiting each instance to 4 cores each, this would then have about 1/3 the core-to-core latency of Intel's new chips.
This ^^^^ AMD has clearly come up with the far better solution, given that Intel's 'Mesh' also doesn't address the low yield huge dies needed to make high core count CPU's.
Its interesting to see this behaviour from Intel, they are behaving like a spoilt child who has just been told for the first time in his life "NO"
There is an arrogance to the way Intel are conducting themselves with regards to AMD's challenge to them.
"How very dare you make a better product than ours, i'm going to tell everyone you smell funny"
Some of our readers might argue that some of these answers have been exposed in leaks – from our perspective, getting confirmation from AMD (even on the minor points) is critical here. We’re going to have to wait until nearer the launch to get the answers to these questions. AMD have reaffirmed they are aiming for an early August launch, with more info at SIGGRAPH in a couple of weeks.
I'm still shocked at the size of the cpu socket![]()