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AMD Zen 3 (5000 Series), rumored 17% IPC gain.

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I could be wrong but here is my logic.

AMD are going to fix some of the issues with the existing design of Zen2 by making the cluster of cores all part of the same ccx.

Great that fixes it for now.

But once the cores/ccxs scale again and we have cpus with 32, 64 + cores/threads we will be back to the same issue of inter ccx latencies.

So replicating the same issue we have now but at a different scale.

Yes... i was about to say something along the lines of.....

By the time that actually matters, I doubt we'll be using Zen, so that's probably the engineering approach of "it works for now, who cares".
 
I could be wrong but here is my logic.

AMD are going to fix some of the issues with the existing design of Zen2 by making the cluster of cores all part of the same ccx.

Great that fixes it for now.

But once the cores/ccxs scale again and we have cpus with 32, 64 + cores/threads we will be back to the same issue of inter ccx latencies.

So replicating the same issue we have now but at a different scale.

This could be OK though for a typical customer - if you can get the core count in a single CCX high enough to enable the best perf/value in gaming then the only people who need to really make that consideration around the latency those who arent just gaming or only need as many cores as a single CCX can offer (most of the market would fit in here I think) - content creators and devs are probably the most interested in the nigher core count parts.

I suppose the cost of a single CCX chip could be lower as well (compared to a multi CCX chip with the same total core count)

It makes sense that CCX core density should trend up over time - as software is becoming increasingly multi-threaded over time as well.
 
If you had a 16c chip 2x 8c chiplets, you disable one for low latency gaming and activate 2 for multi threaded goodness.

Best of both worlds for hopefully a realistic price, low temps and power efficiency.
 
It's been suggested that Zen 4 is having a complete makeover of the chiplet, possibly doing away with the notion of "Compute Complexes" maybe?. That'll get rid of any potential scaling problems pushing the core counts on a chiplet up.

The big latency hit on Zen 2 is having a single chiplet comprised of a pair of CCXs, so despite existing on the same piece of silicon, if 1 CCX wants to talk to other CCX then it has to round trip through the rest of the system. That's going away with Zen 3 having all 8 cores in a single CCX. This is why the 3300X's performance is so exciting: not necessarily for what it can do in and of itself, but what implied performance having a single CCX can bring.

Of course that doesn't change the latency impact of communicating with other chiplets, but the faster the IF, the smaller that impact will be.
 
If you had a 16c chip 2x 8c chiplets, you disable one for low latency gaming and activate 2 for multi threaded goodness.

Best of both worlds for hopefully a realistic price, low temps and power efficiency.
Well Threadripper had similar with game mode, so it's clearly possible at a technical level. Given that a prospective buyer of the 4950X would be after the multi-threaded performance, I don't see why AMD would be inclined to block the ability to switch off a chiplet, it's not like it would cannibalise sales of anything else in the stack.

Would be a great feature to have (and would apply to the 12 core version too).
 
Forgot about threadripper for a second.

Like you say it should be possible on a technical level and the cores have moved on quite a bit from zen. Would be quite something if you had 9900k or greater performance in one mode and with a click of a setting 3950 or greater performance in the other.
 
Who else thinks AMD releasing two CPU's identical to eachother but for the CCX layout was deliberate? I think this is AMD giving us kind of a sneak peek to Zen 3.
Even AMD aren't that oblivious to the world around them. A simultaneous launch means they're going to be reviewed together. In fact, AMD will no doubt have issued reviewer guidance that have both CPUs in it. And be virtue of them being reviewed together, the nuances of cross-CCX communication, the latencies involved and the performance differential will be clear as day because this is a direct apples-to-apples comparison that so far we've not been able to do with Zen 2.

So yes, for those of us nerds paying attention to the fine details, this is definitely a hint as to what Zen 3 will bring: "oh look, this is what Zen 2 can do when it utilises a single CCX in its entirety. Now imagine what twice the core count and a clock bump could do..."
 
too much conspiracy
AMD is harvesting chips where more than 2 cores are not functional. Depending on which ones are disabled, you end up with 1 or 2 CCX setup 4 core CPUs. Alternatively when cache takes a hit in one CCX, you ae left with another.
 
too much conspiracy
AMD is harvesting chips where more than 2 cores are not functional. Depending on which ones are disabled, you end up with 1 or 2 CCX setup 4 core CPUs. Alternatively when cache takes a hit in one CCX, you ae left with another.
Conspiracy? Hardly. Interesting discussion maybe. Consider this: there is no need to go through the expense of creating a Matisse package for junk chiplets when GloFo's 12nm process is so damn cheap.

1600AF is a barnstormer entry-level CPU for little money. It has performance that is somewhat above its price point, and as a 2600 under a different name, it's going to be so cheap to produce on GloFo's 12nm process. Now, TSMC's 7nm yields are so high the overall cost of Zen 2 chiplets is going to be pretty low too, despite the wafer itself costing a lot. Defect rates are pretty low too by all accounts, so I'd be surprised with 2 and 4 core chiplets are actually a common thing. So with plentiful chiplet supply for the 3600 as the bottom Zen 2 offering, and performance tiers under that covered by 1600AF, chiplets with only 2 or 4 functioning cores could just be discarded without a hit on AMD's bottom line.

So why then pay the extra BOM for a Matisse package and I/O die? That Ryzen 3100 is going to cost more to manufacture than the 1600AF and yet performs worse.

You could be sensible and say AMD are wringing every last penny out of their products and materials - if it can be sold, sell it - although I'd be interested to know how the 3100 vs 1600AF stack up in terms of profit margin. You could also be cynical and say this is a big step towards finally cutting ties with GloFo - with no Zen+ products left, they're only making Zen 2 and Zen 3 I/O dies, which will then come to an end with the 7nm I/O die in Zen 4.

But then you could be playful and suggest exactly what we're saying: the 3300X may not make much sense in a profit-generating sense, but as a veiled marketing exercise and little teaser to continue discussion and build hype for Zen 3, it's invaluable. And I genuinely believe this is a factor. May not be the only reason, but it is still one of the reasons.
 
Yes... i was about to say something along the lines of.....

But you see then we come full circle again to what I was saying about ram speeds.

If given the current architecture we end up in a scenario where inter ccx latency becomes an issue again just at a different scale, the FCLK which is the inter ccx fabric becomes the bottleneck again.

Given CURRENTLY there is a penalty having a decoupled FCLK from MCLK then ram speed becomes a way to increase the FLCK clock and hence the inter ccx latencies which we have already established is the issue with the current design.

I fully expect the 4000 series to have a higher FCLK as well as ram speed support. These are easy wins for AMD to get more performance.

The very architecture of Ryzen being multiple ccxs attached via an IF, then in order to keep scaling this they need to keep improving the inter ccx latencies and thus ram speed. Unless they find a way to decouple FCLK from MCLK with out the penalty to latencies.

Additionally if you look at benchmarks you get more fps gains from a higher FCLK than you do from lower timings.

So 3733@CL16 is > 3600@CL14
 
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The consoles will have 8 cores,so if games are being made with 8 cores in mind,I think an 8 core CCX,will be fine for quite a while. The sort of applications which use more than 8 cores don't generally seem to have an issue with latency AFAIK.
 
Don't know but clocking the IF and RAM on the 3300X seems to make little difference, Steve Burk did that and that was his conclusion.
I thought Infinity Fabric only mattered when there are multiple chiplet or CCD on the same die. 3100 and 3300 both only have 1 CCD so there is technically no infinity fabric.

again please stop mention Steve Burke’s. I literally feel sick and throw up everytime I read his name or got a link to his channel. I want to live to a healthy old age still. :).
 
I thought Infinity Fabric only mattered when there are multiple chiplet or CCD on the same die. 3100 and 3300 both only have 1 CCD so there is technically no infinity fabric.

again please stop mention Steve Burke’s. I literally feel sick and throw up everytime I read his name or got a link to his channel. I want to live to a healthy old age still. :).

Yes, it does. 3300X has Infinity fabric but there is no inter-CCX or inter CCD latency. Hence why is faster.
 
3100 and 3300 both only have 1 CCD so there is technically no infinity fabric.
No, 3100 is a pair of chiplets (CCDs) with 6 cores disabled on each, leaving only half a CCX. 3300X is a single chiplet with 4 cores disabled, leaving 1 fully intact CCX. Both CPUs still have to bounce through the IO die over Infinity Fabric, but the 3100 has to also bounce across the Infinity Fabric for the 4 cores to talk to each other. 3300X has no such restriction because all 4 cores are on the same piece of silicon and within the same CCX. It's this particular detail that is so exciting for what Zen 3 can bring with no CCX latency.
 
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